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august 2006 1/135 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. rev 1 ST7L1 8-bit mcu for automotive with single voltage flash/rom memory, data eeprom, adc, 5 timers, spi preliminary data memories ? 4 kbytes single voltage extended flash (xflash) or rom with read-out protection, in- circuit programming and in-application pro- gramming (icp and iap), 10k write/erase cy- cles guaranteed, data retention 20 years at 55c ? 256 bytes ram ? 128 bytes data e2prom with read-out pro- tection, 300k write/erase cycles guaranteed, data retention 20 years at 55c clock, reset and supply management ? enhanced reset system ? enhanced low voltage supervisor (lvd) for main supply and an auxiliary voltage detector (avd) with interrupt ca pability for implement- ing safe power-down procedures ? clock sources: intern al 1% rc oscillator, crystal/ceramic resonator or external clock ? optional x4 or x8 pll for 4 or 8 mhz internal clock (only x8 pll available for rom devices) ? 5 power saving modes: halt, active halt, auto wake-up from halt, wait and slow i/o ports ? up to 17 multifunctional bidirectional i/o lines ?7 high sink outputs 5 timers ? configurable watchdog timer ? two 8-bit lite timers with prescaler, 1 realtime base and 1 input capture ? two 12-bit auto-reload timers with 4 pwm outputs, 1 input capture, 1 pulse and 4 output compare functions communication interface ? spi synchronous serial interface interrupt management ? 12 interrupt vectors plus trap and reset ? 15 external interrupt lines (on 4 vectors) a/d converter ? 7 input channels ? 10-bit precision instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode de- tection ? 17 main addressing modes ? 8 x 8 unsigned multiply instructions development tools ? full hardware/software development package ? dm (debug module) device summary so20 300mil features ST7L15 ST7L19 program memory - bytes 4k ram (stack) - bytes 256 (128) data eeprom - bytes - 128 peripherals lite timer with watchdog, autoreload timer, spi, 10-bit adc operating supply 3v to 5.5v cpu frequency up to 8 mhz (w/ext osc up to 16 mhz and int 1 mhz rc 1%, pllx8/4 mhz) operating temperature up to - 40 to +85c / -40 to +125c packages so20 300mil 1
table of contents 135 2/135 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 5.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 data eeprom read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 6.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 multi-oscillator (mo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 9.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.4 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.5 active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.6 auto wake-up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1
table of contents 3/135 10.4 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.7 device-specific i/o port config uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.8 multiplexed input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2 dual 12-bit autoreload timer 3 (at3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.3 lite timer 2 (lt2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.4 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.5 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.10 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 120 13.11 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14.2 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 126 15.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26 15.2 device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 15.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
ST7L1 4/135 1 introduction the ST7L1 is a member of the st7 microcontroller family suitable for automo tive applications. all st7 devices are based on a common industry-stand- ard 8-bit core, featuring an enhanced instruction set. the ST7L1 features flash memory with byte-by- byte in-circuit programming (icp) and in-applica- tion programming (iap) capability. under software control, the ST7L1 device can be placed in wait, slow or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer bo th power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. for easy reference, all pa rametric data is located in section 13 on page 98 . the ST7L1 features an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm reg- isters, refer to the st7 icc protocol reference manual . figure 1. general block diagram *note : not available on rom devices. 8-bit core alu address and data bus osc1 osc2 reset port a internal clock control ram (256 bytes) pa7:0 (8 bits) v ss v dd power supply program (up to 4 kbytes) lvd, avd memory pll x8 ext. 1 mhz int. 1 mhz 8-bit lite timer 2 port b spi pb6:0 (7 bits) data eeprom (128 bytes) 1% rc osc to 16 mhz adc 12-bit auto-reload timer 2 clkin / 2 or pll x4* watchdog debug module port c pc1:0 (2 bits) 1
ST7L1 5/135 2 pin description figure 2. 20-pin so package pinout notes: 1. this pin cannot be configured as external interrupt in rom devices. 2. osc1 and osc2 are not multiplexed in rom devices and port c is not present. legend / abbreviations for table 1 : type: i = input, o = output, s = supply in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: ? input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog ? output: od = open drain, pp = push-pull the reset configuration of each pi n (shown in bold) is valid as lo ng as the device is in reset state. table 1. device pin description 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v ss v dd ain5/pb5 clkin/ain4/pb4 mosi/ain3/pb3 miso/ain2/pb2 sck/ain1/pb1 s s /ain0/pb0 osc1/clkin/pc0 2) osc2/pc1 2) pa5 (hs)/atpwm3/iccdata pa4 (hs)/atpwm2 pa3 (hs)/atpwm1 pa2 (hs)/atpwm0 pa1 (hs)/atic pa0 (hs)/ltic 1) (hs) 20ma high sink capability eix associated external interrupt vector 12 11 9 10 ain6/pb6 pa7 (hs) pa6/mco/iccclk/break reset ei3 ei2 ei0 ei1 pin no. pin name type level port / control main function (after reset) alternate function so20 input output input output float wpu int ana od pp 1v ss s ground 2v dd s main power supply 3 reset i/o c t x x top priority non maskable interrupt (active low) 1
ST7L1 6/135 notes: 1. this pin cannot be configured as external interrupt in rom devices. 2. osc1 and osc2 are not multiplexed in rom devices and port c is not present. 3. pcor not implemented but p-transistor al ways active in output mode (refer to figure 30 on page 45 ) 4pb0/ain0/ss i/o c t x ei3 xxx port b0 adc analog input 0 or spi slave select (active low) caution: no negative current injec- tion allowed on this pin. 5 pb1/ain1/sck i/o c t x xxx port b1 adc analog input 1 or spi serial clock 6 pb2/ain2/miso i/o c t x xxx port b2 adc analog input 2 or spi master in/ slave out data 7 pb3/ain3/mosi i/o c t x ei2 xxx port b3 adc analog input 3 or spi master out / slave in data 8 1) pb4/ain4/clkin/ compin- i/o c t x xxx port b4 adc analog input 4 or external clock input 9 1) pb5/ain5 i/o c t x xxx port b5 adc analog input 5 10 1) pb6/ain6 i/o c t x xxx port b6 adc analog input 6 11 1) pa7 i/o c t hs x ei1 x x port a7 12 pa6 /mco/ iccclk/break i/o c t x ei1 xx port a6 main clock output or in circuit communication clock or external break caution: during normal operation this pin must be pulled- up, internal- ly or externally (external pull-up of 10k mandatory in noisy environ- ment). this is to avoid entering icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset puts it back in input pull-up 13 pa5 /iccdata/ atpwm3 i/o c t hs x ei1 xx port a5 in circuit communication data or auto-reload timer pwm3 14 pa4/atpwm2 i/o c t hs x xx port a4 auto-reload timer pwm2 15 pa3/atpwm1 i/o c t hs x ei0 xx port a3 auto-reload timer pwm1 16 pa2/atpwm0 i/o c t hs x xx port a2 auto-reload timer pwm0 17 pa1/atic i/o c t hs x xx port a1 auto-reload timer input capture 18 1) pa0/ltic i/o c t hs x xx port a0 lite timer input capture 19 2) osc2/pc1 i/o x x port c1 3) resonator oscillator inverter output 20 2) osc1/clkin/pc0 i/o x x port c0 3) resonator oscillator inverter input or external clock input pin no. pin name type level port / control main function (after reset) alternate function so20 input output input output float wpu int ana od pp 1
ST7L1 7/135 3 register and memory map as shown in figure 3 , the mcu can address 64 kbytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 256 bytes of ram, 128 bytes of data eeprom and up to 4 kbytes of flash program memory. the ram space includes up to 128 bytes for the stack from 180h to 1ffh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see fig- ure 3 ) mapped in the upper part of the st7 ad- dressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). the size of flash sector 0 and other device op- tions are configurable by option byte (refer to sec- tion 15.1 on page 126 ). important: memory locations marked as ?re- served? must never be accessed. accessing a re- served area can have unpredictable effects on the device. figure 3. memory map notes: 1. dee0h, dee1h, dee2h and dee3h addresses are located in a reserved area but are special bytes containing also the rc calibration values which are read-accessible only in user mode. if all the eeprom data or flash space (including the rc calibration values locations) has been erased (after the read out protection removal), then the rc calibration values can still be obtained through these four addresses. 0000h ram flash memory (4k) interrupt and reset vectors hw registers 0080h 007fh 0fffh (see table 2 ) 1000h 107fh ffe0h ffffh (see table 5 ) 0180h reserved 017fh short addressing ram (zero page) 0080h 00ffh (128 bytes) data eeprom (128 bytes) f000h 1080h efffh reserved ffdfh 128 bytes stack 0100h 017fh 1 kbyte 3 kbytes (sector 1) (sector 0) 4k flash ffffh fc00h fbffh f000h program memory dee0h rccrh1 rccrl1 see section 7.1 on page 21 and note 1. 00ffh 01ffh 0100h reserved ram (128 bytes) reserved 0200h 0180h 01ffh dee1h dee2h rccrh0 rccrl0 dee3h 1
ST7L1 8/135 register and memory map (cont?d) table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register ffh 1) 00h 40h r/w r/w r/w 0003h 0004h 0005h port b pbdr pbddr pbor port b data register port b data direction register port b option register ffh 1) 00h 00h r/w r/w r/w 2) 0006h 0007h port c pcdr pcddr port c data register port c data direction register 0xh 00h r/w r/w 0008h 0009h 000ah 000bh 000ch lite timer 2 ltcsr2 ltarr ltcntr ltcsr1 lticr lite timer control/ status register 2 lite timer auto-reload register lite timer counter register lite timer control/ status register 1 lite timer input capture register 00h 00h 00h 0x00 0000b xxh r/w r/w read only r/w read only 000dh 000eh 000fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h auto- reload timer 2 atcsr cntrh cntrl atrh atrl pwmcr pwm0csr pwm1csr pwm2csr pwm3csr dcr0h dcr0l dcr1h dcr1l dcr2h dcr2l dcr3h dcr3l aticrh aticrl atcsr2 breakcr atr2h atr2l dtgr breaken timer control/status register counter register high counter register low auto-reload register high auto-reload register low pwm output control register pwm 0 control/status register pwm 1 control/status register pwm 2 control/status register pwm 3 control/status register pwm 0 duty cycle register high pwm 0 duty cycle register low pwm 1 duty cycle register high pwm 1 duty cycle register low pwm 2 duty cycle register high pwm 2 duty cycle register low pwm 3 duty cycle register high pwm 3 duty cycle register low input capture register high input capture register low timer control/status register 2 break control register auto-reload register 2 high auto-reload register 2 low dead time generation register break enable register 0x00 0000b 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 00h 00h 00h 00h 03h r/w read only read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w read only read only r/w r/w r/w r/w r/w r/w 0027h to 002dh reserved area (7 bytes) 002eh wdg wdgcr watchdog control register 7fh r/w 0002fh flash fcsr flash control/status register 00h r/w 00030h eeprom eecsr data eeprom control/status register 00h r/w 1
ST7L1 9/135 legend : x = undefined, r/w = read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in i nput configuration, the values of the i/o pins are returned in stead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 3. for a description of the debug module registers, see st7 icc protocol reference manual . 0031h 0032h 0033h spi spidr spicr spicsr spi data i/o register spi control register spi control status register xxh 0xh 00h r/w r/w r/w 0034h 0035h 0036h adc adccsr adcdrh adcdrl a/d control status register a/d data register high data low register 00h xxh 0xh r/w read only r/w 0037h itc eicr external interrupt control register 00h r/w 0038h mcc mccsr main clock contro l/status register 00h r/w 0039h 003ah clock and reset rccr sicsr rc oscillator c ontrol register system integrity control/status register ffh 0110 0xx0b r/w r/w 003bh pll clock select plltst pll test register 00h r/w 003ch itc eisr external interrupt selection register 0ch r/w 003dh to 0048h reserved area (12 bytes) 0049h 004ah awu awupr awucsr awu prescaler register awu control/status register ffh 00h r/w r/w 004bh 004ch 004dh 004eh 004fh 0050h 0051h dm 3) dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l dmcr2 dm control register dm status register dm breakpoint register 1 high dm breakpoint register 1 low dm breakpoint register 2 high dm breakpoint register 2 low dm control register 2 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w 0052h to 007fh reserved area (46 bytes) address block register label register name reset status remarks 1
ST7L1 10/135 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on-board using in-circuit programming or in-application program- ming. the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte read-out and write protection 4.3 programming modes the st7 can be programmed in three different ways: ? insertion in a programming tool. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be pro- grammed or erased. ? in-circuit programming. in this mode, flash sectors 0 and 1, option byte row and data eeprom (if present) can be programmed or erased without removing the device from the application board. ? in-application programming. in this mode, sector 1 and data eeprom (if present) can be programmed or erased without removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit commu- nication) which allows an st7 plugged on a print- ed circuit board (pcb) to communicate with an ex- ternal programming device connected via a cable. icp is performed in three steps: ? switch the st7 to icc mode (in-circuit com- munications). this is done by driving a specif- ic signal sequence on the iccclk/data pins while the reset pin is pulled low. when the st7 enters icc mode, it fetches a specific re- set vector which points to the st7 system memory containing the icc protocol routine. this routine enables the st7 to receive bytes from the icc interface. ? download icp driver code in ram from the iccdata pin ? execute icp driver code in ram to program the flash memory depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in-applicatio n programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). iap mode is fully controlled by user software, al- lowing it to be adapted to the user application (such as a user-defined strategy for entering pro- gramming mode or a choice of communications protocol used to fetch the data to be stored). this mode can be used to program any memory areas except sector 0, which is write/erase protected to allow recovery in case errors occur during the pro- gramming operation. 1
ST7L1 11/135 flash program memory (cont?d) 4.4 icc interface icp needs a minimum of four and up to six pins to be connected to the programming tool. these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin ? iccdata: icc input serial data pin ? osc1: main clock input for external source (not required on devices without osc1/osc2 pins) ?v dd : application board power supply (option- al, see note 3) figure 4. typical icc interface notes: 1. if the iccclk or iccdata pins are only used as out- puts in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not availabl e for the application. if they are used as inputs by the applic ation, isolation such as a serial resistor must be im plemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor values. 2. during the icp session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the app lication reset circuit if it drives more than 5ma at hi gh level (push-pull output or pull-up resistor < 1k). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc network with r > 1k or a reset man- agement ic with open dr ain output and pull-up resistor > 1k, no additional components are needed. in all cases the user must ensure that no external reset is gen- erated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be con- nected when using most st programming tools (it is used to monitor the application power supply). please re- fer to the programming tool manual . 4. pin 9 must be connected to the osc1 pin of the st7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. on st7 devices with multi-oscillator capability, osc2 must be grounded in this case. 5. in 38-pulse icc mode, t he internal rc oscillator is forced as a clock source, regardless of the selection in the option byte. for ST7L1 devices which do not support the internal rc oscillator, the ?option byte disabled? mode must be used (35-pulse icc mode entry, clock provided by the tool). caution: during normal operation the iccclk pin must be pulled up, internally or externally (external pull-up of 10k mandatory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. in the application, even if the pin is configured as output, any reset puts it back in input pull-up. icc connector iccdata iccclk reset vdd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) st7 c l2 c l1 osc1 osc2 optional see note 1 see note 1 and caution see note 2 application reset source application i/o (see note 4) 1
ST7L1 12/135 flash program memory (cont?d) 4.5 memory protection there are two different types of memory protec- tion: read-out protection and write/erase protec- tion, which can be applied individually. 4.5.1 read-out protection read-out protection, when selected, protects against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreaka- ble, the feature provides a very high level of pro- tection for a general purpose microcontroller. both program and data e 2 memory are protected. in flash devices, this prot ection is removed by re- programming the option. in this case, both pro- gram and data e 2 memory are automatically erased and the device can be reprogrammed. read-out protection selection depends on the de- vice type: ? in flash devices it is enabled and removed through the fmp_r bit in the option byte. ? in rom devices it is enabled by the mask option specified in the option list. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impos- sible to both overwrite and erase program memo- ry. it does not apply to e 2 data. its purpose is to provide advanced security to applications and pre- vent any change being made to the memory con- tent. warning : once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. write/erase protection is enabled through the fmp_w bit in the option byte. 4.6 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . 4.7 register description flash control/status register (fcsr) read/write reset value: 000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) note: this register is reserved for programming using icp, iap or other programming methods. it controls the xflash programming and erasing op- erations. when an epb or anothe r programming tool is used (in socket or icp mode), the rass keys are sent automatically. 70 00000optlatpgm 1
ST7L1 13/135 5 data eeprom 5.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back- up for storing data. usin g the eeprom requires a basic access protocol described in this chapter. 5.2 main features up to 32 bytes programmed in the same cycle eeprom mono-voltage (charge pump) chained erase and programming cycles internal control of the global programming cycle duration wait mode management readout protection figure 5. eeprom block diagram eecsr high voltage pump 0 e2lat 0 0 0 0 0 e2pgm eeprom memory matrix (1 row = 32 x 8 bits) address decoder data multiplexer 32 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus 1
ST7L1 14/135 data eeprom (cont?d) 5.3 memory access the data eeprom memory read/write access modes are controlled by the e2lat bit of the eep- rom control/status register (eecsr). the flow- chart in figure 6 describes these different memory access modes. read operation (e2lat = 0) the eeprom can be read as a normal rom loca- tion when the e2lat bit of the eecsr register is cleared. on this device, data eepr om can also be used to execute machine code. do not write to the data eeprom while executing from it. this would re- sult in an unexpected code being executed. write operation (e2lat = 1) to access the write mode, the e2lat bit must be set by software (the e2pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 32 data latches ac- cording to its address. when pgm bit is set by the software, all the previ- ous bytes written in the data latches (up to 32) are programmed in the eeprom cells. the effective high address (row) is determined by the last eep- rom write sequence. to avoid wrong program- ming, the user must ensure that all the bytes writ- ten between two programming sequences have the same high address: only the five least signif- icant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously. note : care should be taken during the program- ming cycle. writing to the same memory location over-programs the memory (logical and between the two write access data results) because the data latches are only cleared at the end of the pro- gramming cycle and by the falling edge of the e2lat bit. it is not possible to read the latched data. this note is illustrated by the figure 8 on page 16 . figure 6. data eeprom programming flowchart read mode e2lat = 0 e2pgm = 0 write mode e2lat = 1 e2pgm = 0 read bytes in eeprom area writeupto32bytes in eeprom area (with the same 11 msb of the address) start programming cycle e2lat = 1 e2pgm = 1 (set by software) e2lat 01 cleared by hardware 1
ST7L1 15/135 data eeprom (cont?d) figure 7. data eeprom write operation note: if a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. byte 1 byte 2 byte 32 phase 1 programming cycle read operation impossible phase 2 read operation possible e2lat bit e2pgm bit writing data latches waiting e2pgm and e2lat to fall set by user application cleared by hardware ? row / byte ? 0 1 2 3 ... 30 31 physical address 0 00h...1fh 1 20h...3fh ... n nx20h...nx20h+1fh row definition 1
ST7L1 16/135 data eeprom (cont?d) 5.4 power saving modes wait mode the data eeprom can enter wait mode on ex- ecution of the wfi instruction of the microcontrol- ler or when the microcontroller enters active halt mode.the data eeprom immediately en- ters this mode if there is no programming in progress, otherwise th e data eeprom finishes the cycle and then enters wait mode. active halt mode refer to wait mode. halt mode the data eeprom immediately enters halt mode if the microcontroller executes the halt in- struction. theref ore, the eeprom stops the func- tion in progress, and data may be corrupted. 5.5 access error handling if a read access occurs while e2lat = 1, then the data bus is not driven. if a write access occurs while e2lat = 0, then the data on the bus is not latched. if a programming cycle is interrupted (by reset action), the integrity of the data in memory is not guaranteed. 5.6 data eeprom read-out protection the read-out protection is enabled through an op- tion bit (see option byte section). when this option is selected, the programs and data stored in the eeprom memory are protected against read-out (including a re-write protection). in flash devices, when this protection is removed by reprogramming the option byte, the entire pro- gram memory and eeprom is first automatically erased. note: both program memory and data eeprom are protected using the same option bit. figure 8. data eeprom programming cycle lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage 1
ST7L1 17/135 data eeprom (cont?d) 5.7 register description eeprom control/status register (eec- sr) read/write reset value: 0000 0000 (00h) bits 7:2 = reserved, forced by hardware to 0. bit 1 = e2lat latch access transfer this bit is set by software. it is cleared by hard- ware at the end of the programming cycle. it can only be cleared by software if the e2pgm bit is cleared. 0: read mode 1: write mode bit 0 = e2pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware. 0: programming finished or not yet started 1: programming cycle is in progress note : if the e2pgm bit is cleared during the pro- gramming cycle, the memory data is not guaran- teed table 3. data eeprom register map and reset values 70 000000e2late2pgm address (hex.) register label 76543210 0030h eecsr reset value 000000 e2lat 0 e2pgm 0 1
ST7L1 18/135 6 central processing unit 6.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 6.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 6.3 cpu registers the six cpu registers shown in figure 9 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 9. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 1
ST7L1 19/135 cpu registers (cont?d) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested usin g the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt ro utine is not interruptible because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (that is, the most signif icant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. 70 111hinz c 1
ST7L1 20/135 cpu registers (cont?d) stack pointer (sp) read/write reset value: 01ffh the stack pointer is a 16-bit register which always points to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 10 ). since the stack is 128 bytes deep, the 9 most sig- nificant bits are forced by hardware. following an mcu reset, or after a re set stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by an ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 10 . ? when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. ? on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt occupies five locations in the stack area. figure 10. stack manipulation example 15 8 00000001 70 1 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0180h stack higher address = 01ffh stack lower address = 0180h 1
ST7L1 21/135 7 supply, reset an d clock management the device includes a ran ge of utility features for securing the application in critical situations (for example, in case of a power brown-out) and re- ducing the number of external components. main features clock management ? 1 mhz internal rc oscillator (enabled by op- tion byte ? 1 to 16 mhz external crystal/ceramic resona- tor (selected by option byte) ? external clock input (enabled by option byte) ? pll for multiplying the frequency by 8 or 4 (enabled by option byte). only multiplying by 8 is available for rom devices. reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) with reset generation (enabled by option byte) ? auxiliary voltage dete ctor (avd) with inter- rupt capability for monitoring the main supply (enabled by option byte) 7.1 internal rc oscillator adjustment the device contains an internal rc oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5v to 5.5v). it must be cali- brated to obtain the frequency required in the ap- plication. this is done by the software writing a 10- bit calibration value in the rccr (rc control reg- ister) and in the bits 6:5 in the sicsr (si control status register). whenever the microcontroller is reset, the rccr returns to its default value (ffh), that is, each time the device is reset, the calibration value must be loaded in the rccr. predefined calibration values are stored in eeprom for 3.3v and 5v v dd sup- ply voltages at 25c, as shown in the following ta- ble. note: 1. dee0h, dee1h, dee2h, and dee3h addresses are lo- cated in a reserved area but are special bytes containing also the rc calibration val ues which are read-accessible only in user mode. if all the eeprom data or flash space (including the rc calibrati on value locations) has been erased (after the read-out pr otection removal), then the rc calibration values c an still be obtained through these four addresses. for compatibility reasons with the sicsr register, cr[1:0] bits are stored in the fifth and sixth pos ition of the dee1 and dee3 addresses. notes: ? in 38-pulse icc mode, the internal rc oscillator is forced as a clock source, regardless of the se- lection in the option byte. for ST7L1 devices which do not support the internal rc oscillator, the ?option byte disabled? mode must be used (35-pulse icc mode entry, clock provided by the tool). ? for more information on the frequency and accu- racy of the rc oscillator see ?electrical characteristics? on page 98 . ? to improve clock stabilit y and frequency accura- cy, it is recommended to place a decoupling ca- pacitor, typically 100nf, between the v dd and v ss pins as close as possible to the st7 device. ? these bytes are systematically programmed by st, including on fastrom devices. caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an1324 for information on how to calibrate the rc frequency using an ex- ternal reference signal. rccr conditions ST7L1 address rccrh0 v dd = 5v t a = 25c f rc = 1 mhz dee0h 1) (cr[9:2]) rccrl0 dee1h 1) (cr[1:0]) rccrh1 v dd = 3.3v t a = 25c f rc = 1 mhz dee2h 1) (cr[9:2]) rccrl1 dee3h 1) (cr[1:0]) 1
ST7L1 22/135 supply, reset and clock management (cont?d) 7.2 phase locked loop the pll can be used to multiply a 1 mhz frequen- cy from the rc oscillator or the external clock by 4 or 8 to obtain f osc of 4 or 8 mhz. the pll is ena- bled and the multiplication factor of 4 or 8 is select- ed by 2 option bits: ? the x4 pll is intended for operation with v dd in the 3v to 3.6v range (available only on flash devices) ? the x8 pll is intended for operation with v dd in the 3.6v to 5.5v range 1) refer to section 15.1 for the option byte descrip- tion. if the pll is disabled and the rc oscillator is ena- bled, then f osc =1mhz. if both the rc oscillator and the pll are disabled, f osc is driven by the external clock. figure 11. pll output frequency timing diagram when the pll is started, after reset or wake-up from halt mode or awufh mode, it outputs the clock after a delay of t startup . when the pll output signal reaches the operating frequency, the locked bit in the sicscr register is set. full pll accuracy (acc pll ) is reached after a stabilization time of t stab (see figure 11 and section 13.3.4 on page 105 ) refer to section 7.6.4 on page 30 for a description of the locked bit in the sicsr register. note: 1. it is possible to obtain f osc = 4 mhz in the 3.3v to 5.5v range with internal rc and pll enabled by selecting 1 mhz rc and x8 pll and setting the plldiv2 bit in the plltst register (see section 7.6.4 on page 30 ). 7.3 register description main clock control/status register (mccsr) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved , must be kept cleared. bit 1 = mco main clock out enable this bit is read/write by software and cleared by hardware after a reset. this bit enables the mco output clock. 0: mco clock disabled, i/o port free for general purpose i/o. 1: mco clock enabled. bit 0 = sms slow mode select this bit is read/write by software and cleared by hardware after a reset. this bit selects the input clock f osc or f osc /32. 0: normal mode (f cpu = f osc ) 1: slow mode (f cpu = f osc /32) rc control register (rccr) read / write reset value: 1111 1111 (ffh) bits 7:0 = cr[9:2] rc oscillator frequency ad- justment bits these bits must be written immediately after reset to adjust the rc oscillato r frequency an d to obtain an accuracy of 1%. the application can store the correct value for each voltage range in eeprom and write it to this register at start-up. 00h = maximum available frequency ffh = lowest available frequency these bits are used with the cr[1:0] bits in the sicsr register. refer to section 7.6.4 on page 30 . note: to tune the oscillator, write a series of differ- ent values in the register until the correct frequen- cy is reached. the fastest method is to use a di- chotomy starting with 80h. 4/8 x freq. locked bit set t stab t lock input output freq. t startup t 70 000000 mco sms 70 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 1
ST7L1 23/135 supply, reset and clock management (cont?d) figure 12. clock management block diagram cr6 cr9 cr2 cr3 cr4 cr5 cr8 cr7 rccr f osc mccsr sms mco mco f cpu f cpu to cpu and peripherals (1ms timebase @ 8 mhz f osc ) /32 divider f osc f osc /32 f osc f ltimer 1 0 lite timer 2 counter 8-bit clkin osc2 clkin tunable oscillator 1% rc pll 1 mhz -> 8 mhz pll 1 mhz -> 4 mhz rc osc ck_pllx4x8 /2 divider option bits osc,plloff, clksel[1:0] osc 1-16 mhz clkin clkin /osc1 osc /2 divider osc/2 clkin/2 clkin/2 option bits osc,plloff, clksel[1:0] lock32 cr1 cr0 sicsr plldiv2 /2 plltst plldiv2 0 7 0 7 0 7 1
ST7L1 24/135 supply, reset and clock management (cont?d) 7.4 multi-osc illator (mo) the main clock of the st7 can be generated by four different source types coming from the multi- oscillator block (1 to 16 mhz): an external source 5 different configurations for crystal or ceramic resonator oscillators an internal high frequency rc oscillator each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. the associated hardware configurations are shown in table 4 . refer to sec- tion 13 electrical characteristics for more details. external clock source in external clock mode, a clock signal (square, si- nus or triangle) with ~50% duty cycle must drive the osc1 pin while the osc2 pin is tied to ground. note: when the multi-oscillato r is not used, pb4 is selected by default as the external clock. crystal/ceramic oscillators in this mode, with a self-controlled gain feature, an oscillator of any frequen cy from 1 to 16 mhz can be placed on osc1 and osc2 pins. this family of oscillators has t he advantage of producing a very accurate rate on the main clock of the st7. in this mode of the multi-oscillato r, the resonator and the load capacitors must be placed as close as possi- ble to the oscillator pins to minimize output distor- tion and start-up stabilizat ion time. the loading ca- pacitance values must be adjusted according to the selected oscillator. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. internal rc oscillator in this mode, the tunable 1% rc oscillator is the main clock source. the tw o oscillator pins must be tied to ground if dedicat ed to oscillator use, other- wise they are general purpose i/o. the calibration is done through the rccr[7:0] and sicsr[6:5] registers. table 4. st7 clock sources hardware configuration external clock crystal/ceramic resonators internal rc oscillator osc1 osc2 external st7 source osc1 osc2 load capacitors st7 c l2 c l1 osc1 osc2 st7 1
ST7L1 25/135 supply, reset and clock management (cont?d) 7.5 reset sequence manager (rsm) 7.5.1 introduction the reset sequence manager includes three re- set sources as shown in figure 14 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset note: a reset can also be triggered following the detection of an illegal opcode or prebyte code. re- fer to section 12.2.1 on page 95 for further details. these sources act on the reset pin which is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of three phases as shown in figure 13 : active phase depending on the reset source 256 or 4096 cpu clock cycle delay (see table below) reset vector fetch the 256 or 4096 cpu clock cycle delay allows the oscillator to stabilize an d ensures that recovery has taken place from the reset state. the short- er or longer clock cycle delay is automatically se- lected depending on the clock source chosen by option byte: the reset vector fetch phase duration is two clock cycles. if the pll is enabled by option byte, it outputs the clock after an additional delay of t startup (see figure 11 ). figure 13. reset sequence phases 7.5.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see section 13 electrical characteristics for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 15 ). this de- tection is asynchronous and therefore the mcu can enter the reset stat e even in halt mode. figure 14. reset block diagram clock source cpu clock cycle delay internal rc oscillator 256 external clock (connected to clkin pin) 256 external crystal/ceramic oscillator (connected to osc1/osc2 pins) 4096 reset active phase internal reset 256 or 4096 clock cycles fetch vector reset r on v dd watchdog reset lvd reset internal reset pulse generator filter illegal opcode reset 1) note 1 : see ?illegal opcode reset? on page 95 for more details on ille gal opcode reset conditions. 1
ST7L1 26/135 supply, reset and clock management (cont?d) the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in section 13 electrical characteristics . 7.5.3 external power-on reset if the lvd is disabled by the option byte, to start up the microcontroller correctly, the user must use an external reset circuit to ensure that the reset signal is held low until v dd is over the minimum level specified for the selected f osc frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the reset pin. 7.5.4 internal low voltage detector (lvd) reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd ST7L1 27/135 supply, reset and clock management (cont?d) 7.6 system integrity management (si) the system integrity management block contains the low voltage detector (lvd) and auxiliary volt- age detector (avd) functions. it is managed by the sicsr register. note: a reset can also be triggered following the detection of an illegal opcode or prebyte code. re- fer to section 12.2.1 on page 95 for further details. 7.6.1 low voltage detector (lvd) the low voltage detector (lvd) function gener- ates a static reset when the v dd supply voltage is below a v it-(lvd) reference value. this means that it secures the power-up as well as the power- down, keeping the st7 in reset. the v it-(lvd) reference value for a voltage drop is lower than the v it+(lvd) reference value for power- on to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hystere- sis). the lvd reset circuitry generates a reset when v dd is below: ?v it+(lvd) when v dd is rising ?v it-(lvd) when v dd is falling the lvd function is illustrated in figure 16 . provided the minimum v dd value (guaranteed for the oscillator frequency) is above v it-(lvd) , the mcu can only be in two modes: ? under full software control ? in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage de tector reset, the reset pin is held low, thus permitting the mcu to reset other devices. notes : the lvd allows the device to be used without any external reset circuitry. the lvd is an optional function which can be se- lected by the option byte. use of lvd with capacitive power supply: with this type of power supply, if power cuts occur in the ap- plication, it is recommended to pull v dd down to 0v to ensure optimum restart conditions. refer to circuit example in figure 96 on page 119 and note 4. for the application to function correctly, it is rec- ommended to make sure that the v dd supply volt- age rises monotonously when the device is exiting from reset. figure 16. low voltage detector vs reset v dd v it+ (lvd) reset v it- (lvd) v hys 1
ST7L1 28/135 supply, reset and clock management (cont?d) figure 17. reset and supply management block diagram 7.6.2 auxiliary voltage detector (avd) the auxiliary voltage dete ctor (avd) function is based on an analog comparison between a v it- (avd) and a v it+(avd) reference value and the v dd main supply voltage (v avd ). the v it-(avd) refer- ence value for falling volt age is lower than the v it+(avd) reference value for rising voltage in or- der to avoid parasitic detection (hysteresis). the output of the avd comparator is directly read- able by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. caution : the avd functions only if the lvd is en- abled through the option byte. 7.6.2.1 monitoring the v dd main supply if the avd interrupt is enabled, an interrupt is gen- erated when the voltage crosses the v it+(lvd) or v it-(avd) threshold (avdf bit is set). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing the software to shut down safely before the lvd resets the micro- controller. see figure 18 on page 29 . low voltage detector (lvd) auxiliary voltage detector (avd) reset v ss v dd reset sequence manager (rsm) avd interrupt request system integrity management watchdog sicsr timer (wdg) avdie avdf status flag 0 0 lvdrf locked wdgrf 0 1
ST7L1 29/135 supply, reset and clock management (cont?d) figure 18. using the avd to monitor v dd 7.6.3 low-power modes 7.6.3.1 interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is re- set (rim instruction). v dd v it+(avd) v it-(avd) avdf bit 01 reset if avdie bit = 1 v hyst avd interrupt request interrupt cleared by v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 0 1 hardware interrupt cleared by reset mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. the avd remains active. interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no 1
ST7L1 30/135 supply, reset and clock management (cont?d) 7.6.4 register description system integrity (si) control/status register (sicsr) read/write reset value: 0110 0xx0 (6xh) bit 7 = reserved (should be 0) bits 6:5 = cr[1:0] rc oscillator frequency ad- justment bits these bits, as well as cr[9:2] bits in the rccr register must be written immediately after reset to adjust the rc oscillator fr equency and to obtain an accuracy of 1%. refer to section 7.3 on page 22 . bit 4 = wdgrf watchdog reset flag this bit indicates that the last reset was generat- ed by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is give n in the following table. bit 3 = locked pll locked flag this bit is set and cleared by hardware. it is set au- tomatically when the pll reaches its operating fre- quency. 0: pll not locked 1: pll locked bit 2 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared by software (by reading). when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 1 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is gen- erated when the avdf bit is set. refer to figure 18 and to section 7.6.2.1 for additional details. 0: v dd over avd threshold 1: v dd under avd threshold bit 0 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag is set. the pending interrupt information is automati- cally cleared when software enters the avd inter- rupt routine. 0: avd interrupt disabled 1: avd interrupt enabled application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. pll test register (plltst) read/write reset value: 0000 0000(00h) bit 7: plldiv2 pll clock divide by 2 this bit is read or write by software and cleared by hardware after reset. this bit divides the pll out- put clock by 2. 0: pll output clock 1: divide by 2 of pll output clock refer to ?clock management block diagram? on page 23 note: write of this bit is effective after 2 tcpu cy- cles (if system clock is 8 mhz) or else 1 cycle (if system clock is 4 mhz), that is, effective time is 250ns. bits 6:0: reserved , must always be cleared. 70 res cr1 cr0 wdgrf locked lvdrf avdf avdie reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x 70 plldiv2 0 0 0 0 0 0 0 1
ST7L1 31/135 8 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 19 . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? the i bit of the cc register is set to prevent addi- tional interrupts. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which caus es the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit is cleared and the main program resumes. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the interrupt map- ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi- cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the ?exit from halt? column in th e interrupt mapping ta- ble). 8.1 non maskable software interrupt this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it is serviced according to the flowchart in figure 19 . 8.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to le ave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt tr iggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. caution: the type of sensitivity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. in case of a nanded source (as described in the i/o ports section), a low level on an i/o pin, configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity. 8.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ? the i bit of the cc register is cleared. ? the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: ? writing ?0? to the corresponding bit in the status register or ? access to the status register while the flag is set followed by a read or write of an associated reg- ister. note : the clearing sequence resets the internal latch. a pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear se- quence is executed. 1
ST7L1 32/135 interrupts (cont?d) figure 19. interrupt processing flowchart table 5. interrupt mapping notes: 1. this interrupt exits the mcu from ?auto wake-up from halt? mode only. 2. these interrupts exit the mcu from ?active halt? mode only. n source block description register label priority order exit from halt or awufh address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 awu auto wake-up interrupt awucsr yes 1) fffah-fffbh 1 ei0 external interrupt 0 n/a yes fff8h-fff9h 2 ei1 external interrupt 1 fff6h-fff7h 3 ei2 external interrupt 2 fff4h-fff5h 4 ei3 external interrupt 3 fff2h-fff3h 5 lite timer lite timer rtc2 interrupt ltcsr2 no fff0h-fff1h 6 not used ffeeh-ffefh 7 si avd interrupt sicsr no ffech-ffedh 8 at timer at timer output compare interrupt or input capture interrupt pwmxcsr or atcsr no ffeah-ffebh 9 at timer overflow interrupt atcsr yes 2) ffe8h-ffe9h 10 lite timer lite timer input capture interrupt ltcsr no ffe6h-ffe7h 11 lite timer rtc1 interrupt ltcsr yes 2) ffe4h-ffe5h 12 spi spi peripheral interrupts spicsr yes ffe2h-ffe3h 13 at timer at timer overflow interrupt atcsr2 no ffe0h-ffe1h i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending? 1
ST7L1 33/135 interrupts (cont?d) external interrupt control register (eicr) read/write reset value: 0000 0000 (00h) bits 7:6 = is3[1:0] ei3 sensitivity these bits define the interrupt sensitivity for ei3 (port b0) according to table 6 . bits 5:4 = is2[1:0] ei2 sensitivity these bits define the interrupt sensitivity for ei2 (port b3) according to table 6 . bits 3:2 = is1[1:0] ei1 sensitivity these bits define the interrupt sensitivity for ei1 (port a7) according to table 6 . bits 1:0 = is0[1:0] ei0 sensitivity these bits define the interrupt sensitivity for ei0 (port a0) according to table 6 . notes: 1. these 8 bits can be written only when the i bit in the cc register is set. 2. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. refer to section ?external interrupt function? on page 43 table 6. interrupt sensitivity bits . external interrupt selection regis- ter (eisr) read/write reset value: 0000 1100 (0ch) bits 7:6 = ei3[1:0] ei3 pin selection these bits are written by software. they select the port b i/o pin used for the ei3 external interrupt ac- cording to the table below. external interrupt i/o pin selection * reset state bits 5:4 = ei2[1:0] ei2 pin selection these bits are written by software. they select the port b i/o pin used for the ei2 external interrupt ac- cording to the table below. external interrupt i/o pin selection * reset state notes: 1. pb4 cannot be used as an external interrupt in halt mode. 70 is31 is30 is21 is20 is11 is10 is01 is00 isx1 isx0 external interrupt sensitivity 0 0 falling edge and low level 1 rising edge only 1 0 falling edge only 1 rising and falling edge 70 ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00 ei31 ei30 i/o pin 00 pb0* 0 1 pb1 1 0 pb2 ei21 ei20 i/o pin 0 0pb3* 1 pb4 1) 1 0 pb5 1 pb6 1
ST7L1 34/135 interrupts (cont?d) bits 3:2 = ei1[1:0] ei1 pin selection these bits are written by software. they select the port a i/o pin used for the ei1 external interrupt ac- cording to the table below. external interrupt i/o pin selection * reset state bits 1:0 = ei0[1:0] ei0 pin selection these bits are written by software. they select the port a i/o pin used for the ei0 external interrupt ac- cording to the table below. external interrupt i/o pin selection * reset state ei11 ei10 i/o pin 0 0 pa4 1 pa5 1 0 pa6 1 pa7* ei01 ei00 i/o pin 0 0pa0* 1 pa1 1 0 pa2 1 pa3 1
ST7L1 35/135 9 power saving modes 9.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, five main pow- er saving modes are implemented in the st7 (see figure 20 ): slow wait (and slow-wait) active halt auto wake-up from halt (awufh) halt after a reset, the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency di vided or multiplied by 2 (f osc2 ). from run mode, the different power saving modes can be selected by setting the relevant reg- ister bits or by calling the specific st7 software in- struction whose action de pends on the oscillator status. figure 20. power saving mode transitions 9.2 slow mode this mode has two targets: ? to reduce power consumption by decreasing the internal clock in the device, ? to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillato r frequency is divided by 32. the cpu and peripherals are clocked at this lower frequency. note : slow-wait mode is activated when enter- ing wait mode while the device is already in slow mode. figure 21. slow mode clock transition power consumption wait slow run active halt high low slow wait auto wake-up from halt halt sms f cpu normal run mode request f osc f osc /32 f osc 1
ST7L1 36/135 power saving modes (cont?d) 9.3 wait mode wait mode places the mcu into a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i bit of the cc register is cleared to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon it wakes up and the program counter branches to the start- ing address of the interrupt or reset service rou- tine. refer to figure 22 . figure 22. wait mode flowchart notes: 1. before servicing an interrupt , the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and clear ed when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 0 on cpu oscillator peripherals ibit on on x 1) on cycle delay 256 or 4096 cpu clock 1
ST7L1 37/135 power saving modes (cont?d) 9.4 halt mode the halt mode is the lo west power consumption mode of the mcu. it is entered by executing the ?halt? instruction when active halt is disabled (see section 9.5 on page 38 for more details) and when the awuen bit in the awucsr register is cleared. the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 5, ?interrupt mapping,? on page 32 ) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immedi ately turned on and the 256 or 4096 cpu cycle delay is used to stabilize the oscillator. after the st art-up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see fig- ure 24 ). when entering halt mode, the i bit in the cc reg- ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up im- mediately. in halt mode, the main oscillator is turned off, stopping all internal processing, including the op- eration of the on-chip peripherals. all peripherals are not clocked except those which receive their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of wa tchdog operation with halt mode is configured by the ?wdghalt? op- tion bit of the option byte. the halt instruction, when executed while the watchdog system is en- abled, can generate a watchdog reset (see sec- tion 15.1 on page 126 for more details). figure 23. halt timing overview figure 24. halt mode flowchart notes: 1. wdghalt is an option bit. see option byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). refer to table 5, ?interrupt mapping,? on page 32 for more details. 4. before servicing an interrupt , the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and clear ed when the cc register is popped. 5. if the pll is enabled by option byte, it outputs the clock after a delay of t startup (see figure 11 on page 22 ). halt run run 256 or 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [active halt disabled] reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off x 4) on cpu oscillator peripherals ibit on on x 4) on 256 or 4096 cpu clock delay 5) watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle halt instruction (active halt disabled) (awucsr.awuen=0) 1
ST7L1 38/135 power saving modes (cont?d) 9.4.1 halt mode recommendations ? make sure that an external event is available to wake up the microcontroller from halt mode. ? when using an external interrupt to wake up the microcontroller, re-initialize the corresponding i/o as ?input pull-up with interrupt? before exe- cuting the halt instruction. the main reason for this is that the i/o may be incorrectly configured due to external interference or by an unforeseen logical condition. ? for the same reason, re-initialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in pro- gram memory with the value 0x8e. ? as the halt instruction clears the interrupt mask in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits be- fore executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corre- sponding to the wake-up event (reset or external interrupt). 9.5 active halt mode active halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the ?halt? in- struction. the decision to enter either in active halt or halt mode is given by the ltcsr/atc- sr register status as shown in the following table: the mcu exits active halt mode on reception of a specific interrupt (see table 5, ?interrupt map- ping,? on page 32 ) or a reset. ? when exiting active halt mode by means of a reset, a 256 or 4096 cpu cycle delay oc- curs. after the start-up delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 26 ). ? when exiting active halt mode by means of an interrupt, the cpu immediately resumes oper- ation by servicing the inte rrupt vector which woke it up (see figure 26 ). when entering active halt mode, the i bit in the cc register is cleared to enable interrupts. there- fore, if an interrupt is pending, the mcu wakes up immediately (see note 3). in active halt mode, on ly the main oscillator and the selected timer counter (lt/at) are running to keep a wake-up time base. all other peripherals are not clocked except those which receive their clock supply from another clock generator (such as external or auxiliary oscillator). note: as soon as active halt is enabled, exe- cuting a halt instruction while the watchdog is active does not generate a reset. this means that the device cannot exceed a de- fined delay in this power saving mode. figure 25. active halt timing overview ltcsr1 tb1ie bit atcsr ovfie bit atcsr ck1 bit atcsr ck0 bit meaning 0 x x 0 active halt mode disabled 0x 1 xxx active halt mode enabled x 101 halt run run 256 or 4096 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [active halt enabled] 1
ST7L1 39/135 power saving modes (cont?d) figure 26. active halt mode flowchart notes: 1. this delay occurs only if the mcu exits active halt mode by means of a reset. 2. peripherals clocked with an ex ternal clock source can still be active. 3. only the rtc1 interrupt and some specific interrupts can exit the mcu from active halt mode. refer to table 5, ?interrupt mapping,? on page 32 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and clear ed when the cc register is popped. 9.6 auto wake-up from halt mode auto wake-up from halt (awufh) mode is simi- lar to halt mode with the addition of a specific in- ternal rc oscillator for wake-up (auto wake-up from halt oscillator). compared to active halt mode, awufh has lower power consumption (the main clock is not kept running but there is no accu- rate realtime clock available). it is entered by executing the halt instruction when the awuen bit in the awucsr register has been set. figure 27. awufh mode block diagram as soon as halt mode is entered and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divid- er and a programmable prescaler controlled by the awupr register. the output of this prescaler pro- vides the delay time. when the delay has elapsed, the awuf flag is set by hardware and an interrupt wakes up the mcu from halt mode. at the same time, the main oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. after this start-up delay, the cpu resumes oper- ation by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects f awu_rc to the input capture of the 12-bit auto-re- load timer, allowing the f awu_rc to be measured using the main oscillator cl ock as a reference time- base. halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals 2) ibit on off x 4) on cpu oscillator peripherals ibit on on x 4) on 256 or 4096 cpu clock delay (active halt enabled) (awucsr.awuen=0) cycle awu rc awufh f awu_rc awufh (ei0 source) oscillator prescaler/1 .. 255 interrupt /64 divider to timer input capture 1
ST7L1 40/135 power saving modes (cont?d) similarities with halt mode the following awufh mode behavior is the same as normal halt mode: ? the mcu can exit awufh mode by means of any interrupt with exit from halt capability or a re- set (see section 9.4 halt mode ). ? when entering awufh mode, the i bit in the cc register is forced to 0 to enable interrupts. there- fore, if an interrupt is pending, the mcu wakes up immediately. ? in awufh mode, the main oscillator is turned off, stopping all internal processing, including the operation of the on-chip peripherals. none of the peripherals are clocked except those which re- ceive their clock supply from another clock gen- erator (such as an extern al or auxiliary oscillator like the awu oscillator). ? the compatibility of watchdog operation with awufh mode is configured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction, when executed while the watchdog system is enabled, can gen- erate a watchdog reset. figure 28. awuf halt timing diagram awufh interrupt f cpu run mode halt mode 256 or 4096 t cpu run mode f awu_rc clear by software t awu 1
ST7L1 41/135 power saving modes (cont?d) figure 29. awufh mode flowchart notes: 1. wdghalt is an option bit. see option byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only an awufh interrupt and some specific interrupts can exit the mcu from halt mode (such as external in- terrupt). refer to table 5, ?interrupt mapping,? on page 32 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc register are set to the current software priority level of t he interrupt routine and recovered when the cc register is popped. 5. if the pll is enabled by t he option byte, it outputs the clock after an additional delay of t startup (see figure 11 ). reset interrupt 3) y n n y cpu main osc peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx 4) on cpu main osc peripherals i[1:0] bits on on xx 4) on 256 or 4096 cpu clock delay 5) watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (active halt disabled) (awucsr.awuen=1) 1
ST7L1 42/135 power saving modes (cont?d) 9.6.0.1 register description awufh control/status register (awucsr) read/write reset value: 0000 0000 (00h) bits 7:3 = reserved . bit 1 = awuf auto wake-up flag this bit is set by hardw are when the awu module generates an interrupt and cleared by software on reading awucsr. writing to this bit does not change its value. 0: no awu interrupt occurred 1: awu interrupt occurred bit 1 = awum auto wake-up measurement this bit enables the aw u rc oscillator and con- nects its output to the input capture of the 12-bit auto-reload timer. this allows the timer to meas- ure the awu rc oscillator dispersion and then compensate this dispersion by providing the right value in the awupre register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto wake-up from halt enabled this bit enables the auto wake-up from halt fea- ture: once halt mode is entered, the awufh wakes up the microcontroller after a time delay de- pendent on the awu prescaler value. it is set and cleared by software. 0: awufh (auto wake-up from halt) mode disa- bled 1: awufh (auto wake-up from halt) mode ena- bled awufh prescaler register (awupr) read/write reset value: 1111 1111 (ffh) bits 7:0 = awupr[7:0] auto wake-up prescaler these 8 bits define the awupr dividing factor (as explained below: in awu mode, the period that the mcu stays in halt mode (t awu in figure 28 on page 40 ) is de- fined by this prescaler register can be programmed to modify the time that the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, depending on the product, an interrupt is generated immediately after a halt instruction or the awupr remains unchanged. table 7. awu register map and reset values 70 00000awufawumawuen 70 awup r7 awup r6 awup r5 awup r4 awup r3 awup r2 awup r1 awup r0 awupr[7:0 ] dividing factor 00h forbidden 01h 1 ... ... feh 254 ffh 255 t awu 64 awupr 1 f awurc ------------------------- -t rcstrt + = address (hex.) register label 76543210 0049h awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1 004ah awucsr reset value 0 0 0 0 0 awuf awum awuen 1
ST7L1 43/135 10 i/o ports 10.1 introduction the i/o ports allow data transfer. an i/o port con- tains up to eight pins. each pin can be pro- grammed independently either as a digital input or digital output. in addition, specific pins may have several other functions. these functions can in- clude external interrupt, alternate signal input/out- put for on-chip peripherals or analog input. 10.2 functional description a data register (dr) and a data direction regis- ter (ddr) are always associated with each port. the option register (or) , which allows input/out- put options, may or may not be implemented. the following description take s into account the or register. refer to the port configuration table for device specific information. an i/o pin is programmed using the corresponding bits in the ddr, dr and or registers: bit x corre- sponding to pin x of the port. figure 30 shows the generic i/o block diagram. 10.2.1 input modes clearing the ddrx bit selects input mode. in this mode, reading its dr bit returns the digital value from that i/o pin. if an or bit is available, different input modes can be configured by software: floating or pull-up. re- fer to section 10.3 i/o port implementation for configuration. notes : 1. writing to the dr modifies the latch value but does not change the state of the input pin. 2. do not use read/mod ify/write instructions (bset/bres) to modify the dr register. 10.2.1.1 external interrupt function external interrupt capabilit y is selected using the eisr register. if eisr bits are <> 0, the corre- sponding pin is used as external interrupt. in this case, the orx bit can select the pin as either inter- rupt floating or interrupt pull-up. in this configura- tion, a signal edge or level input on the i/o gener- ates an interrupt request via the corresponding in- terrupt vector (eix). falling or rising edge sens itivity is programmed in- dependently for each interrupt vector. the exter- nal interrupt control register (eicr) or the miscel- laneous register controls this sensitivity, depend- ing on the device. a device may have up to seven external interrupts. several pins may be tied to one external interrupt vector. refer to ?pin description? on page 5 to see which ports have external interrupts. if several i/o interrupt pins on the same interrupt vector are selected simultaneously, they are logi- cally combined. for this re ason, if one of the inter- rupt pins is tied low, it may mask the others. external interrupts are hardware interrupts. fetch- ing the corresponding interrupt vector automatical- ly clears the request latch. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. spurious interrupts when enabling/disabling an external interrupt by setting/resetting the related or register bit, a spu- rious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. this is due to the edge detector input, which is switched to '1' when the external interrupt is disa- bled by the or register. to avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) must be selected before changing the or register bit and configuring the appropriate sensitivity again. caution: if a pin level change occurs during these operations (asynchronous signal input), as inter- rupts are generated according to the current sen- sitivity, it is advised to disable all interrupts before and to re-enable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. this corresponds to the following steps: 1. to enable an external interrupt: ? set the interrupt mask with the sim instruction (in cases where a pin level change could oc- cur) ? select rising edge ? enable the external interrupt through the or register ? select the desired sensitivity if different from rising edge ? reset the interrupt mask with the rim instruc- tion (in cases where a pin level change could occur) 2. to disable an external interrupt: 1
ST7L1 44/135 i/o ports (cont?d) ? set the interrupt mask with the sim instruction sim (in cases where a pin level change could occur) ? select falling edge ? disable the external interrupt through the or register ? select rising edge ? reset the interrupt mask with the rim instruc- tion (in cases where a pin level change could occur) 10.2.2 output modes setting the ddrx bit select s output mode. writing to the dr bits applies a digital value to the i/o through the latch. reading the dr bits returns the previously stored value. if an or bit is available, different output modes can be selected by software: push-pull or open- drain. refer to ?i/o port implementation? on page 47 for configuration. dr value and output pin status 10.2.3 alternate functions many st7 i/os have one or more alternate func- tions. these may include output signals from, or input signals to, on-chip peripherals. the device pin description table describes which peripheral signals can be input/output to which ports. a signal coming from an on-chip peripheral can be output on an i/o. to do this, enable the on-chip peripheral as an output (enable bit in the peripher- al?s control register). the peripheral configures the i/o as an output and takes priority over standard i/ o programming. the i/o?s state is readable by ad- dressing the corresponding i/o data register. configuring an i/o as floating enables alternate function input. it is not recommended to configure an i/o as pull-up as this increases current con- sumption. before using an i/o as an alternate in- put, configure it without interrupt. otherwise spuri- ous interrupts can occur. configure an i/o as input floating for an on-chip peripheral signal which can be input and output. caution : i/os which can be configured as both an analog and digital alternate function need special attention. the user must control the peripherals so that the signals do not arrive at the same time on the same pin. if an external clock is used, only the clock alternate function should be employed on that i/o pin and not the other alternate function. dr push-pull open-drain 0v ol v ol 1v oh floating 1
ST7L1 45/135 i/o ports (cont?d) figure 30. i/o port general block diagram table 8. port mode options legend : off - implemented not activated on - implemented and activated dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external request (ei x ) interrupt sensitivity selection cmos schmitt trigger register access bit from on-chip periphera l to on-chip peripheral note : refer to the port configuration table for device specific information. combinational logic configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off 1
ST7L1 46/135 i/o ports (cont?d) table 9. i/o configurations notes: 1. when the i/o port is in input conf iguration and the associated alternate function is enabl ed as an output, reading the dr register reads the alter nate function output status. 2. when the i/o port is in output confi guration and the associated al ternate function is enabled as an input, the alternate function reads the pin status giv en by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) condition pad external interrupt polarity data b u s interrupt dr register access w r from other pins source (ei x ) selection dr register alternate input analog input to on-chip peripheral combinational logic pad data bus dr dr register access r/w register pad data b u s dr dr register access r/w alternate alternate enable output register bit from on-chip periphera l 1
ST7L1 47/135 i/o ports (cont?d) analog alternate function configure the i/o as floating input to use an adc input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the adc input. analog recommendations do not change the voltage level or loading on any i/o while conversion is in progress. do not have clocking pins located close to a selected analog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 10.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific i/o port features such as adc input or open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 31 . other transitions are potentially risky and should be avoided, since they may present unwanted side-effects such as spurious interrupt generation. figure 31. interrupt i/o port state transitions 10.4 unused i/o pins unused i/o pins must be connected to fixed volt- age levels. refer to section 13.8 on page 113 . 10.5 low-power modes 10.6 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and if the i bit in the cc register is cleared (rim instruction). related documentation spi communication between st7 and eeprom (an970) s/w implementation of i2c bus master (an1045) software lcd driver (an1048) 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes 1
ST7L1 48/135 i/o ports (cont?d) 10.7 device-specific i/o port configuration the i/o port register configurations are summa- rized as follows: standard ports pa7:0, pb6:0 pc1:0 (multiplexed with osc1,osc2) the selection between osc1 or pc0 and osc2 or pc1 is done by the option byte (refer to section 15.1 on page 126 ). interrupt capability is not avail- able on pc1:0. port c is not present on rom devices. note: pcor not implemented but p-transistor al- ways active in output mode (refer to figure 30 on page 45 ). interrupt ports ports where the external interrupt capability is selected using the eisr register table 10. port configuration (standard ports) note: on ports where the external interrupt capability is selected using the eisr regi ster, the configuration is as follows: table 11. i/o port register map and reset values mode ddr or floating input 0 0 pull-up input 1 open drain output 1 0 push-pull output 1 mode ddr floating input 0 push-pull output 1 mode ddr or floating input 0 0 pull-up interrupt input 1 open drain output 1 0 push-pull output 1 port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up open drain push-pull port b pb6:0 port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:0 floating pull-up interrupt open drain push-pull port b pb6:0 address (hex.) register label 76543210 0000h padr reset value msb 1111111 lsb 1 0001h paddr reset value msb 0000000 lsb 0 1
ST7L1 49/135 10.8 multiplexed input/output ports osc1/pc0 are multiplexed on one pin (pin20) and osc2/pc1 are multiplexed on another pin (pin19). 0002h paor reset value msb 0100000 lsb 0 0003h pbdr reset value msb 1111111 lsb 1 0004h pbddr reset value msb 0000000 lsb 0 0005h pbor reset value msb 0000000 lsb 0 0006h pcdr reset value msb 0000001 lsb 1 0007h pcddr reset value msb 0000000 lsb 0 address (hex.) register label 76543210 1
ST7L1 50/135 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset upon expiration of a programmed time period, unless the program re- freshes the counter?s contents before the t6 bit is cleared. 11.1.2 main features programmable free-running downcounter (64 increments of 16000 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte 11.1.3 functional description the counter value stored in the cr register (bits t[6:0]) is decremented every 16000 machine cy- cles and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low th e reset pin for typically 30s. figure 32. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 16000 t1 t2 t3 t4 t5 1
ST7L1 51/135 on-chip peripherals (cont?d) the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. this downcounter is free- running: it counts down, even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see table 12 .watchdog timing ): ? the wdga bit is set (watchdog enabled). ? the t6 bit is set to prevent generating an imme- diate reset. ? the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. following a reset, the watchdog is disabled. once activated, it can be disabled only by a reset. the t6 bit can generate a software reset (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction generates a reset. table 12.watchdog timing notes: 1. the timing variation shown in table 12 is due to the unknown status of the prescaler when writing to the cr register. 2. the number of cpu clock cycles applied during the reset phase (256 or 4096) must be taken into account in addition to these timings. 11.1.4 hardware watchdog option if hardware watchdog is selected by the option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the option byte description in section 15 on page 126 . 11.1.4.1 using halt mode with the wdg (wdghalt option) if halt mode with watchdog is enabled by the op- tion byte (no watchdog reset on halt instruction), it is recommended before executing the halt in- struction to refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller (same behavior in active halt mode). 11.1.5 interrupts none. 11.1.6 register description control register (wdgcr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bits 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 13. watchdog timer register map and reset values f cpu = 8 mhz wdg counter code min [ms] max [ms] c0h 1 2 ffh 127 128 70 wdga t6 t5 t4 t3 t2 t1 t0 address (hex.) register label 76543210 002eh wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 1
ST7L1 52/135 11.2 dual 12-bit autoreload timer 3 (at3) 11.2.1 introduction the 12-bit autoreload timer can be used for gen- eral-purpose timing functi ons. it is based on one or two free-running 12-bit upcounters with an input capture register and four pwm output channels. there are seven external pins: ? 4 pwm outputs ? atic/ltic pins for the input capture function ? break pin for forcing a break condition on the pwm outputs 11.2.2 main features single timer or dual timer mode with two 12-bit upcounters (cntr1/cntr2) and two 12-bit autoreload registers (atr1/atr2) maskable overflow interrupts pwm mode ? generation of four independent pwmx signals ? dead time generation for half-bridge driving mode with programmable dead time ? frequency 2 khz to 4 mhz (@ 8 mhz f cpu ) ? programmable duty-cycles ? polarity control ? programmable output modes output compare mode input capture mode ? 12-bit input capture register (aticr) ? triggered by rising and falling edges ? maskable ic interrupt ? long range input capture break control flexible clock control one pulse mode on pwm2/3 (available only on flash devices) force update (available only on flash devices) figure 33. single timer mode (encntr2 = 0) pwm0 pwm1 pwm2 pwm3 dead time generator pwm3 duty cycle generator 12-bit input capture pwm2 duty cycle generator pwm1 duty cycle generator pwm0 duty cycle generator 12-bit autoreload register 1 12-bit upcounter 1 output compare cmp interrupt ovf1 interrupt edge detection circuit oe0 oe1 oe2 oe3 dte bit bpen bit break function atic clock control f cpu lite timer 1 ms from off 1
ST7L1 53/135 dual 12-bit autoreload timer 3 (cont?d) figure 34. dual timer mode (encntr2 = 1) pwm0 pwm1 pwm2 pwm3 dead time generator pwm3 duty cycle generator 12-bit input capture 12-bit autoreload register 2 12-bit upcounter 2 pwm2 duty cycle generator pwm1 duty cycle generator pwm0 duty cycle generator 12-bit autoreload register 1 12-bit upcounter 1 output compare cmp interrupt ovf1 interrupt ovf2 interrupt edge detection circuit oe0 oe1 oe2 oe3 atic dte bit bpen bit break function ltic op_en bit clock control f cpu one pulse mode output compare cmp interrupt lite timer 1 ms from off 1
ST7L1 54/135 dual 12-bit autoreload timer 3 (cont?d) 11.2.3 functional description 11.2.3.1 pwm mode this mode allows up to four pulse width modulat- ed signals to be generated on the pwmx output pins. pwm frequency the four pwm signals can have the same fre- quency (f pwm ) or can have two different frequen- cies. this is selected by the encntr2 bit which enables single timer or dual timer mode (see fig- ure 33 and figure 34 ). the frequency is controlled by the counter period and the atr register value. in dual timer mode, pwm2 and pwm3 can be generated with a differ- ent frequency controlled by cntr2 and atr2. f pwm = f counter / (4096 - atr) following the above formula, ? if f counter is 4 mhz , the maximum value of f pwm is 2 mhz (atr register value = 4094),the minimum value is 1 khz (atr register value = 0). ? if f counter is 32 mhz , the maximum value of f pwm is 8 mhz (atr register value = 4092), the minimum value is 8 khz (atr register value = 0). notes: 1. the maximum value of atr is 4094 because it must be lower than the dc4r value, which in this case must be 4095. 2. to update the dcrx registers at 32 mhz, the following precautions must be taken: ? if the pwm frequency is < 1 mhz and the tranx bit is set asynchronously, it should be set twice after a write to the dcrx registers. ? if the pwm frequency is > 1 mhz, the tranx bit should be set along with forcex bit with the same instruction (use a load instruction and not two bset instructions). duty cycle the duty cycle is selected by programming the dcrx registers. these are preload registers. the dcrx values are transfer red in active duty cycle registers after an overflow event if the correspond- ing transfer bit (tranx bit) is set. the tran1 bit controls the pwmx outputs driven by counter 1 and the tran2 bit controls the pwmx outputs driven by counter 2. pwm generation and output compare are done by comparing these active dcrx values with the counter. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (4096 - atr) where atr is equal to 0. with this maximum reso- lution, 0% and 100% duty cycle can be obtained by changing the polarity. at reset, the counter starts counting from 0. when an upcounter overflow occurs (ovf event), the preloaded duty cycle values are transferred to the active duty cycle registers and the pwmx sig- nals are set to a high level. when the upcounter matches the active dcrx value, the pwmx sig- nals are set to a low level. to obtain a signal on a pwmx pin, the contents of the corresponding ac- tive dcrx register must be greater than the con- tents of the atr register. note for rom devices only: the pwm can be enabled/disabled only in overflow isr, otherwise the first pulse of pwm can be different from ex- pected one because no force overflow function is present. the maximum value of atr is 4094 because it must be lower than the d cr value, which in this case must be 4095. polarity inversion the polarity bits can be used to invert any of the four output signals. the inversion is synchronized with the counter overflow if the corresponding transfer bit in the atcsr2 register is set (reset value). see figure 35 . figure 35. pwm polarity inversion the data flip flop (dff) applies the polarity inver- sion when triggered by the counter overflow input. output control the pwmx output signals can be enabled or disa- bled using the oex bits in the pwmcr register. pwmx pwmx pin counter overflow opx pwmxcsr register inverter dff tranx atcsr2 register 1
ST7L1 55/135 dual 12-bit autoreload timer 3 (cont?d) figure 36. pwm function figure 37. pwm signal from 0% to 100% duty cycle duty cycle register auto-reload register pwmx output t 4095 000 with oe=1 and opx=0 (atr) (dcrx) with oe=1 and opx=1 counter counter pwmx output t with mod00=1 and opx=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcrx=000h dcrx=ffdh dcrx=ffeh dcrx=000h atr= ffdh f counter pwmx output with mod00=1 and opx=1 1
ST7L1 56/135 dual 12-bit autoreload timer 3 (cont?d) 11.2.3.2 dead time generation a dead time can be inserted between pwm0 and pwm1 using the dtgr regi ster. this is required for half-bridge driving where pwm signals must not be overlapped. the non-overlapping pwm0/ pwm1 signals are generated through a program- mable dead time by setting the dte bit. dead time value = dt[6:0] x tcounter1 dtgr[7:0] is buffered in side so as to avoid de- forming the current pwm cycle. the dtgr effect will take place only after an overflow. notes: 1. dead time is generated only when dte = 1 and dt[6:0] 0 . if dte is set and dt[6:0] = 0, pwm output signals will be at their reset state. 2. half-bridge driving is po ssible only if polarities of pwm0 and pwm1 are not inverted, that is, if op0 and op1 are not set. if polarity is inverted, overlapping pwm0/pwm1 signals will be generat- ed. 3. dead time generation does not work at 1msec timebase. figure 38. dead time generation in the above example, when the dte bit is set: ? pwm goes low at dcr0 ma tch and goes high at atr1+tdt ? pwm1 goes high at dcr0+tdt and goes low at atr match. with this programmable delay (tdt), the pwm0 and pwm1 signals which are generated are not overlapped. dcr0+1 atr1 dcr0 t dt t dt t dt = dt[6:0] x t counter1 pwm 0 pwm 1 cntr1 ck_cntr1 t counter1 ovf pwm 0 pwm 1 if dte = 0 if dte = 1 counter = dcr0 counter = dcr1 1
ST7L1 57/135 dual 12-bit autoreload timer 3 (cont?d) 11.2.3.3 break function the break function can be used to perform an emergency shutdown of the application being driv- en by the pwm signals. the break function is activated by the external break pin. in order to us e the break function it must be previously enabled by software setting the bpen bit in the breakcr register. the break active level can be programmed by the bredge bit in the breakcr register (in rom devices the active level is not programmable; the break active level is low level). when an active lev- el is detected on the br eak pin, the ba bit is set and the break function is activated. in this case, the pwm signals are forced to break value if the respective oex bit is set in the pwmcr register. software can set the ba bit to activate the break function without using the break pin. the bren1 and bren2 bits in the breaken register are used to enable the break activation on the two counters respectively. in dual timer mode, the break for pwm2 and pwm3 is enabled by the bren2 bit. in single timer mode, the bren1 bit enables the break for all pwm channels. in rom devices, bren1 and bren2 are both forced by hardware at high level and all pwms are enabled. when a break function is activated (ba bit = 1 and bren1/bren2 = 1): ? the break pattern (pwm[3:0] bits in the breakcr is forced directly on the pwmx output pins if respective oex is set (after the inverter). ? the 12-bit pwm counter cntr1 is put to its re- set value, that is 00h (if bren1 = 1). ? the 12-bit pwm counter cntr2 is put to its re- set value, that is 00h (if bren2 = 1). ? atr1, atr2, preload and active dcrx are put to their reset values. ? counters stop counting. when the break function is deactivated after ap- plying the break (ba bit goes from 1 to 0 by soft- ware), the timer takes the control of the pwm ports. figure 39. block diagram of break function pwm0 pwm1 pwm2 pwm3 pwm0 pwm1 pwm2 pwm3 breakcr register break pin (inverters) pwm0 pwm1 pwm2 pwm3 bpen ba level selection bredge breakcr register encntr2 bit bren1 bren2 breaken register pwm0/1 break enable pwm2/3 break enable oex 1
ST7L1 58/135 dual 12-bit autoreload timer 3 (cont?d) 11.2.3.4 output compare mode to use this function, load a 12-bit value in the preload dcrxh and dcrxl registers. when the 12-bit upcounter cntr1 reaches the value stored in the active dcrxh and dcrxl reg- isters, the cmpfx bit in the pwmxcsr register is set and an interrupt request is generated if the cmpie bit is set. in single timer mode the output compare function is performed only on cntr1. the difference be- tween both the modes is that in single timer mode, cntr1 can be compared with any of the four dcr registers, and in dual timer mode, cntr1 is compared with dcr0 or dcr1 and cntr2 is compared with dcr2 or dcr3. in rom devices, the cntr2 counte r is not used for this comparison. notes: 1. the output compare function is only available for dcrx values other than 0 (reset value). 2. duty cycle registers are buffered internally. the cpu writes in preload duty cycle registers and these values are transferred to active duty cycle registers after an overflow event if the corre- sponding transfer bit (tranx bit) is set. output compare is done by comparing these active dcrx values with the counters. figure 40. block diagram of out put compare mode (single timer) dcrx output compare circuit counter 1 (atcsr) cmpie preload duty cycle reg0/1/2/3 active duty cycle regx cntr1 tran1 (atcsr2) ovf (atcsr) cmpfx (pwmxcsr) cmp request interrupt 1
ST7L1 59/135 dual 12-bit autoreload timer 3 (cont?d) 11.2.3.5 input capture mode the 12-bit aticr register is used to latch the val- ue of the 12-bit free running upcounter cntr1 af- ter a rising or falling edge is detected on the atic pin. when an input capture occurs, the icf bit is set and the aticr register contains the value of the free running upcounter. an ic interrupt is gen- erated if the icie bit is set. the icf bit is reset by reading the aticrh/aticrl register when the icf bit is set. the aticr is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. any further input capture is inhibited while the icf bit is set. figure 41. block diagram of input capture mode figure 42. input capture timing diagram atcsr ck0 ck1 icie icf 12-bit autoreload register 12-bit upcounter1 f cpu atic 12-bit input capture register ic interrupt request atr1 aticr cntr1 (1 ms f ltimer @ 8 mhz) timebase off counter1 t 01h f counter xxh 02h 03h 04h 05h 06h 07h 04h atic pin icf flag interrupt 08h 09h 0ah interrupt aticr read 09h 1
ST7L1 60/135 dual 12-bit autoreload timer 3 (cont?d) long input capture pulses that last more than 8 s can be measured with an accuracy of 4 s if f osc = 8 mhz under the following conditions: ? the 12-bit at3 timer is clocked by the lite timer (rtc pulse: ck[1:0] = 01 in the atcsr register) ? the ics bit in the atcsr2 register is set so that the ltic pin is used to trigger the at3 timer cap- ture. ? the signal to be captured is connected to ltic pin ? input capture registers lticr, aticrh and aticrl are read this configuration allows to cascade the lite timer and the 12-bit at3 timer to get a 20-bit input cap- ture value. refer to figure 43 . figure 43. long range input capture block diagram notes: 1. since the input capture flags (icf) for both tim- ers (at3 timer and lt timer) are set when signal transition occurs, software must mask one inter- rupt by clearing the corresponding icie bit before setting the ics bit. 2. if the ics bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the input capture signal because of different values on ltic and atic. to avoid this situation, it is recommend- ed to do the following: ? first, reset both icie bits. ? then set the ics bit. ? reset both icf bits. ? finally, set the icie bit of desired interrupt. 3. how to compute a pulse length with long input capture feature: as both timers are used, computing a pulse length is not straight-forward. the procedure is as fol- lows: ? at the first input capture on the rising edge of the pulse, we assume that values in the registers are as follows: lticr = lt1 aticrh = ath1 aticrl = atl1 hence aticr1 [11:0] = ath1 & atl1 refer to figure 44 on page 61 . lt i c at i c ics 1 0 12-bit input capture register off f cpu f lt i m e r 12-bit upcounter1 12-bit autoreload register 8-bit input c apture register 8-bit timebase counter1 f osc/32 lticr cntr1 aticr atr1 8 lsb bits 12 msb bits lite timer 12-bit artimer 20 cascaded bits 1
ST7L1 61/135 dual 12-bit autoreload timer 3 (cont?d) ? at the second input capt ure on the falling edge of the pulse, we assume that the values in the reg- isters are as follows: lticr = lt2 aticrh = ath2 aticrl = atl2 hence aticr2 [11:0] = ath2 & atl2 now pulse width p between first capture and sec- ond capture will be: p = decimal (f9 ? lt1 + lt2 + 1) * 0.004ms + dec- imal ((fff * n) + n + aticr2 - aticr1 ? 1) * 1ms where n = no of overflows of 12-bit cntr1. figure 44. long range input capture timing diagram f9h 00h lt1 f9h 00h lt2 ath1 & atl1 00h 0h lt1 ath1 lt2 ath2 f osc/32 tb counter1 cntr1 ltic lticr aticrh 00h atl1 atl2 aticrl aticr = aticrh[3:0] & aticrl[7:0] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ath2 & atl2 _ _ _ 1
ST7L1 62/135 dual 12-bit autoreload timer 3 (cont?d) 11.2.3.6 one pulse mode (available only on flash devices) one pulse mode can be used to control pwm2/3 signal with an external ltic pin. this mode is available only in dual timer mode that is only for cntr2, when the op_en bit in pwm3csr regis- ter is set. one pulse mode is activated by the external ltic input. the active edge of the ltic pin is selected by the opedge bit in the pwm3csr register. after obtaining the active edge of the ltic pin, cntr2 is reset (000h) and pwm3 is set to high. cntr2 starts counting from 000h and when it reaches the active dcr3 value, pwm3 goes low. until this time, any further transitions on the ltic signal will have no effect. if there are ltic transi- tions after cntr2 reaches the dcr3 value, cntr2 is reset again and pwm3 goes high. if there are no more ltic active edges after the first active edge, cntr2 counts until it reaches the arr2 value, it is then reset and pwm3 is set to high. the counter again starts counting from 000h. when it reaches the active dcr3 value, pwm3 goes low, after which the counter counts until it reaches arr2, it is reset and pwm3 is set to high again, and the cycle continues in this manner. the same operation applie s for pwm2, but in this case the comparison is done on dcr2 op_en and opedge bits take effect on the fly and are not synchronized with the counter 2 over- flow. the output bit op2/3 can be used to invert the po- larity of pwm2/3 in one pulse mode. the update of these bits (op2/3) is synchronized with the counter 2 overflow, provided the tran2 bit is set. notes : 1. the time taken from activation of ltic input and cntr2 reset is between 1 and 2 t cpu cycles, that is 125n to 250ns (with 8 mhz f cpu ). 2. to avoid spurious interrupts, the litetimer input capture interrupt should be disabled while 12-bit artimer is in one pulse mode. 3. priority of various conditions is as follows for pwm3: break > one pulse mode with active ltic edge > forced overflow by s/w > one pulse mode without active ltic edge > normal pwm operation. 4. it is possible to u pdate dcr2/3 and op2/3 at the counter 2 reset because the update is syn- chronized with the counter reset. this is managed by the overflow interrupt which is generated if the counter is reset either due to arr match or active pulse at ltic pin. 5. dcr2/3 and op2/3 update in one pulse mode is done dynamically using force update in soft- ware. 6. dcr3 update in this mode is not synchronized with any event. that may lead to a longer next pwm3 cycle duration than expected just after the change (refer to figure 47 ). 7. in one pulse mode, the atr2 value must be greater than the dcr2/3 value for pwm2/3 (oppo- site to normal pwm mode). 8. if there is an active edge on the ltic pin after the counter has reset due to an arr2 match, then the timer again is reset and appears as modified duty cycle, depending on whether the new dcr value is less than or more than the previous value. 9. the tran2 bit should be set along with the force2 bit with the same instruction after a write to the dcr register. 10. arr2 value should be changed after an over- flow in one pulse mode to avoid any irregular pwm cycle. 11. when exiting from one pulse mode, the op_en bit in the pwm3csr register should be reset first and then the encntr2 bit (if counter 2 must be stopped). how to enter one pulse mode: 1. load atr2h/atr2l with required value. 2. load dcr3h/dcr3l for pwm3. atr2 value must be greater than dcr3. 3. set op3 in pwm3csr if polarity change is re- quired. 4. select cntr2 by setting encntr2 bit in atcsr2. 5. set tran2 bit in atcsr2 to enable transfer. 6. "wait for overflow" by checking the ovf2 flag in atcsr2. 7. select counter clock using ck<1:0> bits in atc- sr. 8. set op_en bit in pwm3csr to enable one pulse mode. 9. enable pwm3 by oe3 bit of pwmcr. the "wait for overflow" in step 6 can be replaced by forced update. follow the same procedure for pwm2 with the bits corresponding to pwm2. note: when break is applied in one pulse mode, dual 12-bit autoreload timer 3, cntr2, dcr2/3 and atr2 registers are reset. conse- 1
ST7L1 63/135 dual 12-bit autoreload timer 3 (cont?d) quently, these registers must be initialized again when break is removed. figure 45. block diagram of one pulse mode figure 46. one pulse mode timing diagram figure 47. dynamic dcr2/3 update in one pulse mode ltic pin edge selection opedge pwm3csr register op_en 12-bit autoreload register 2 12-bit upcounter 2 12-bit active dcr2/3 generation pwm op2/3 pwm2/3 ovf at r 2 cntr2 lti c pwm2/3 000 dcr2/3 000 dcr2/3 atr2 000 ovf atr2 dcr2/3 ovf atr2 dcr2/3 cntr2 lti c pwm2/3 f counter2 f counter2 op_en = 0 op_en = 1 cntr2 lti c 000 f counter2 op_en = 1 (dcr2/3) old (dcr2/3) new dcr2/3 force2 tran2 fff (dcr3) old (dcr3) new atr2 000 pwm2/3 extra pwm3 period due to dcr3 update dynamically in one pulse mode. 1
ST7L1 64/135 dual 12-bit autoreload timer 3 (cont?d) 11.2.3.7 force update (available only on flash devices) in order not to wait for the counter x overflow to load the value into active dcrx registers, a pro- grammable counter x overflow is provided. for both counters, a separate bit is provided which when set, starts the counters with the overflow val- ue, that is fffh. after overflow, the counters start counting from their respective autoreload register values. these bits are force1 and force2 in the atcsr2 register. force1 is used to force an overflow on counter 1 and force2 is used for counter 2. these bits are set by software and re- set by hardware after the respective counter over- flow event has occurred. this feature can be used at any time. all related features such as pwm generation, output com- pare, input capture and one pulse can be used this way. figure 48. force overflow timing diagram 11.2.4 low power modes 11.2.5 interrupts note: the cmp and at3 ic events are connected to the same interrupt vector. the ovf event is mapped on a separate vector (see interrupts chap- ter). they generate an interrupt if the enable bit is set in the atcsr register and the interrupt mask in the cc register is reset (rim instruction). fff arrx e04 e03 f cntrx cntrx forcex force2 force1 atcsr2 register mode description wait no effect on at timer halt at timer halted interrupt event event flag enable control bit exit from wait exit from halt exit from active halt overflow event ovf1 ovfie1 yes no yes at3 ic event icf icie no cmp event cmpfx cmpie overflow event2 ovf2 ovfie2 1
ST7L1 65/135 dual 12-bit autoreload timer 3 (cont?d) 11.2.6 register description timer control status register (atcsr) read / write reset value: 0x00 0000 (x0h) bit 7 = reserved, must be kept cleared bit 6 = icf input capture flag this bit is set by hardware and cleared by software by reading the aticr register (a read access to aticrh or aticrl will clear this flag). writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred bit 5 = icie ic interrupt enable this bit is set and cleared by software. 0: input capture interrupt disabled 1: input capture interrupt enabled bits 4:3 = ck[1:0] counter clock selection these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. bit 2 = ovf1 overflow flag this bit is set by hardware and cleared by software by reading the atcsr register. it indicates the transition of the counter cntr1 from fffh to atr1 value. 0: no counter overflow occurred 1: counter overflow occurred bit 1 = ovfie1 overflow interrupt enable this bit is read/write by software and cleared by hardware after a reset. 0: overflow interrupt disabled. 1: overflow interrupt enabled. bit 0 = cmpie compare interrupt enable this bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set. 0: output compare interrupt disabled. 1: output compare interrupt enabled. counter register 1 high (cntr1h) read only reset value: 0000 0000 (00h) counter register 1 low (cntr1l) read only reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared bits 11:0 = cntr1[11:0] counter value this 12-bit register is read by software and cleared by hardware after a reset. the counter cntr1 in- crements continuously as soon as a counter clock is selected. to obtain the 12-bit cntr1 value, software should read the counter value in two con- secutive read operations, lsb first. when a coun- ter overflow occurs, the counter restarts from the value specified in the atr1 register. 70 0 icf icie ck1 ck0 ovf1 ovfie1 cmpie counter clock selection ck1 ck0 off 0 0 f ltimer (1 ms timebase @ 8 mhz) 0 1 f cpu 10 15 8 0000 cntr1_ 11 cntr1_ 10 cntr1_ 9 cntr1_ 8 70 cntr1_ 7 cntr1_ 6 cntr1_ 5 cntr1_ 4 cntr1_ 3 cntr1_ 2 cntr1_ 1 cntr1_ 0 1
ST7L1 66/135 dual 12-bit autoreload timer 3 (cont?d) autoreload register (atr1h) read / write reset value: 0000 0000 (00h) autoreload register (atr1l) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared bits 11:0 = atr1[11:0] autoreload register 1 this is a 12-bit register which is written by soft- ware. the atr1 register value is automatically loaded into the upcounter cntr1 when an over- flow occurs. the register value is used to set the pwm frequency. pwm output control register (pwmcr) read/write reset value: 0000 0000 (00h) bits 7:0 = oe[3:0] pwmx output enable . these bits are set and cleared by software and cleared by hardware after a reset. 0: pwm mode disabled. pwmx output alternate function disabled (i/o pin free for general purpose i/o) 1: pwm mode enabled pwmx control status register (pwmxcsr) read / write reset value: 0000 0000 (00h) bits 7:4 = reserved , must be kept cleared bit 3 = op_en one pulse mode enable (not appli- cable to rom devices) this bit is read/write by software and cleared by hardware after a reset. this bit enables the one pulse feature for pwm2 and pwm3. (only availa- ble for pwm3csr) 0: one pulse mode disable for pwm2/3. 1: one pulse mode enable for pwm2/3. bit 2 = opedge one pulse edge selection (not applicable to rom devices) this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the ltic signal for one pulse feature. this bit will be effective only if op_en bit is set. (only available for pwm3csr) 0: falling edge of ltic is selected. 1: rising edge of ltic is selected. bit 1 = opx pwmx output polarity this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the pwm signal. 0: the pwm signal is not inverted. 1: the pwm signal is inverted. bit 0 = cmpfx pwmx compare flag this bit is set by hardware and cleared by software by reading the pwmxcsr register. it indicates that the upcounter value matches the active dcrx register value. 0: upcounter value does not match dcrx value. 1: upcounter value matches dcrx value. 15 8 0 0 0 0 atr11 atr10 atr9 atr8 70 atr7 atr6 atr5 atr4 atr3 atr2 atr1 atr0 70 0 oe3 0 oe2 0 oe1 0 oe0 70 0 0 0 0 op_en opedge opx cmpfx 1
ST7L1 67/135 dual 12-bit autoreload timer 3 (cont?d) break control register (breakcr) read/write reset value: 0000 0000 (00h) bit 7 = reserved, must be kept cleared bit 6 = bredge break input edge selection (not applicable to rom devices) this bit is read/write by software and cleared by hardware after reset. it selects the active level of break signal. 0: low level of break selected as active level. 1: high level of break selected as active level. bit 5 = ba break active this bit is read/write by software, cleared by hard- ware after reset and set by hardware when the break pin is low. it acti vates/deactivates the break function. 0: break not active 1: break active bit 4 = bpen break pin enable this bit is read/write by software and cleared by hardware after reset. 0: break pin disabled 1: break pin enabled bits 3:0 = pwm[3:0] break pattern these bits are read/write by software and cleared by hardware after a reset. they are used to force the four pwmx output signals into a stable state when the break function is active and correspond- ing oex bit is set. pwmx duty cycle register high (dcrxh) read / write reset value: 0000 0000 (00h) pwmx duty cycle register low (dcrxl) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared bits 11:0 = dcrx[11:0] pwmx duty cycle value this 12-bit value is writ ten by software. it defines the duty cycle of the corresponding pwm output signal (see figure 36 ). in pwm mode (oex = 1 in the pwmcr register) the dcr[11:0] bits define the duty cycle of the pwmx output signal (see figure 36 ). in output compare mode, they define the value to be com- pared with the 12-bit upcounter value. input capture register high (aticrh) read only reset value: 0000 0000 (00h) input capture register low (aticrl) read only reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared 70 0 bredge ba bpen pwm3 pwm2 pwm1 pwm0 15 8 0 0 0 0 dcr11 dcr10 dcr9 dcr8 70 dcr7 dcr6 dcr5 dcr4 dcr3 dcr2 dcr1 dcr0 15 8 0 0 0 0 icr11 icr10 icr9 icr8 70 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 1
ST7L1 68/135 dual 12-bit autoreload timer 3 (cont?d) bits 11:0 = icr[11:0] input capture data this is a 12-bit register which is readable by soft- ware and cleared by hardware after a reset. the aticr register contains the captured value of the 12-bit cntr1 register when a rising or falling edge occurs on the atic or ltic pin (depending on ics). capture will only be performed when the icf flag is cleared. break enable register (breaken) read/write reset value: 0000 0011 (03h) bits 7:2 = reserved, must be kept cleared bit 1 = bren2 break enable for counter 2 (forced at high level in rom devices) this bit is read/write by software. it enables the break functionality for counter 2 if ba bit is set in breakcr. it controls pw m2/3 if encntr2 bit is set. 0: no break applied for cntr2 1: break applied for cntr2 bit 0 = bren1 break enable for counter 1 (forced at high level in rom devices) this bit is read/write by software. it enables the break functionality for counter 1. if ba bit is set, it controls pwm0/1 by default, and controls pwm2/3 also if encntr2 bit is reset. 0: no break applied for cntr1 1: break applied for cntr1 timer control register2 (atcsr2) read/write reset value: 0000 0011 (03h) bit 7 = force2 force counter 2 overflow (not applicable to rom devices) this bit is read/set by so ftware. when set, it loads fffh in the cntr2 register. it is reset by hard- ware one cpu clock cycle after counter 2 over- flow has occurred. 0: no effect on cntr2 1: loads fffh in cntr2 note: this bit must not be reset by software bit 6 = force1 force counter 1 overflow (forced at high level in rom devices) this bit is read/set by software. when set, it loads fffh in cntr1 register. it is reset by hardware one cpu clock cycle after counter 1 overflow has occurred. 0: no effect on cntr1 1: loads fffh in cntr1 note: this bit must not be reset by software bit 5 = ics input capture shorted this bit is read/write by software. it a llows the at- timer cntr1 to use the ltic pin for long input capture. 0: atic for cntr1 input capture 1: ltic for cntr1 input capture bit 4 = ovfie2 overflow interrupt 2 enable this bit is read/write by software and controls the overflow interrupt of counter 2. 0: overflow interrupt disabled 1: overflow interrupt enabled bit 3 = ovf2 overflow flag this bit is set by hardware and cleared by software by reading the atcsr2 register. it indicates the transition of the counter 2 from fffh to atr2 val- ue. 0: no counter overflow occurred 1: counter overflow occurred bit 2 = encntr2 enable counter 2 for pwm2/3 this bit is read/write by software and switches the pwm2/3 operation to the cntr2 counter. if this bit is set, pwm2/3 will be generated using cntr2. 0: pwm2/3 is generated using cntr1. 1: pwm2/3 is generated using cntr2. note: counter 2 becomes frozen when the encntr2 bit is reset. when encntr2 is set again, the counter will restar t from the last value. 70 000000bren2bren1 70 force 2 force 1 ics ovfie2 ovf2 encnt r2 tran2 tran1 1
ST7L1 69/135 dual 12-bit autoreload timer 3 (cont?d) bit 1 = tran2 transfer enable 2 this bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. it controls the transfers on cntr2. it allows the value of the preload dcrx registers to be transferred to the active dcrx registers after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. notes: 1. dcr2/3 transfer is co ntrolled using this bit if encntr2 bit is set. 2. this bit must not be reset by software. bit 0 = tran1 transfer enable 1 this bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. it controls the transfers on cntr1. it allows the value of the preload dcrx registers to be transferred to the active dcrx reg- isters after the next overflow event. the opx bits are transferred to the shadow opx bits in the same way. notes: 1. dcr0,1 transfers are always controlled using this bit. 2. dcr2/3 transfer is co ntrolled using this bit if encntr2 is reset. 3.this bit must not be reset by software autoreload register2 (atr2h) read / write reset value: 0000 0000 (00h) autoreload register2 (atr2l) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared bits 11:0 = atr2[11:0] autoreload register 2 this is a 12-bit register which is written by soft- ware. the atr2 register value is automatically loaded into the upcounter cntr2 when an over- flow of cntr2 occurs. the register value is used to set the pwm2/pwm3 frequency when encntr2 is set. dead time generator register (dtgr) read/write reset value: 0000 0000 (00h) bit 7 = dte dead time enable this bit is read/write by software. it enables a dead time generation on pwm0/pwm1. 0: no dead time insertion. 1: dead time insertion enabled. bits 6:0 = dt[6:0] dead time value these bits are read/write by software. they define the dead time inserted between pwm0/pwm1. dead time is calculated as follows: dead time = dt[6:0] x tcounter1 note: 1. if dte is set and dt[6:0] = 0, pwm output sig- nals are at their reset state. 15 8 0 0 0 0 atr11 atr10 atr9 atr8 70 atr7 atr6 atr5 atr4 atr3 atr2 atr1 atr0 70 dte dt6 dt5 dt4 dt3 dt2 dt1 dt0 1
ST7L1 70/135 dual 12-bit autoreload timer 3 (cont?d) table 14. register map and reset values address (hex.) register label 765 4 3 2 1 0 0d atcsr reset value 0 icf 0 icie 0 ck1 0 ck0 0 ovf1 0 ovfie1 0 cmpie 0 0e cntr1h reset value 000 0 cntr1_11 0 cntr1_10 0 cntr1_9 0 cntr1_8 0 0f cntr1l reset value cntr1_7 0 cntr1_8 0 cntr1_7 0 cntr1_6 0 cntr1_3 0 cntr1_2 0 cntr1_1 0 cntr1_0 0 10 atr1h reset value 000 0 atr11 0 atr10 0 atr9 0 atr8 0 11 atr1l reset value atr7 0 atr6 0 atr5 0 atr4 0 atr3 0 atr2 0 atr1 0 atr0 0 12 pwmcr reset value 0 oe3 0 0 oe2 0 0 oe1 0 0 oe0 0 13 pwm0csr reset value 000 0 0 0 op0 0 cmpf0 0 14 pwm1csr reset value 000 0 0 0 op1 0 cmpf1 0 15 pwm2csr reset value 000 0 0 0 op2 0 cmpf2 0 16 pwm3csr reset value 000 0 op_en 0 opedge 0 op3 0 cmpf3 0 17 dcr0h reset value 000 0 dcr11 0 dcr10 0 dcr9 0 dcr8 0 18 dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 19 dcr1h reset value 000 0 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1a dcr1l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1b dcr2h reset value 000 0 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1c dcr2l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1d dcr3h reset value 000 0 dcr11 0 dcr10 0 dcr9 0 dcr8 0 1e dcr3l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1f aticrh reset value 000 0 icr11 0 icr10 0 icr9 0 icr8 0 20 aticrl reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 1
ST7L1 71/135 21 atcsr2 reset value force2 0 force1 0 ics 0 ovfie2 0 ovf2 0 encntr2 0 tran2 1 tran1 1 22 breakcr reset value brsel 0 bredge 0 ba 0 bpen 0 pwm3 0 pwm2 0 pwm1 0 pwm0 0 23 atr2h reset value 000 0 atr11 0 atr10 0 atr9 0 atr8 0 24 atr2l reset value atr7 0 atr6 0 atr5 0 atr4 0 atr3 0 atr2 0 atr1 0 atr0 0 25 dtgr reset value dte 0 dt6 0 dt5 0 dt4 0 dt3 0 dt2 0 dt1 0 dt0 0 26 breaken reset value 0 0 0 0 0 0 bren2 1 bren1 1 address (hex.) register label 765 4 3 2 1 0 1
ST7L1 72/135 11.3 lite timer 2 (lt2) 11.3.1 introduction the lite timer can be used for general-purpose timing functions. it is based on two free-running 8- bit upcounters and an 8-bit input capture register. 11.3.2 main features realtime clock ? one 8-bit upcounter 1 ms or 2 ms timebase period (@ 8 mhz f osc ) ? one 8-bit upcounter with autoreload and pro- grammable timebase period from 4s to 1.024ms in 4s increments (@ 8 mhz f osc ) ? 2 maskable timebase interrupts input capture ? 8-bit input capture register (lticr) ? maskable interrupt with wake-up from halt mode capability figure 49. lite timer 2 block diagram ltcsr1 8-bit timebase /2 8-bit f ltimer 8 ltic f osc /32 tb1f tb1ie tb icf icie lttb1 interrupt request ltic interrupt request lticr input capture register 1 0 1 or 2 ms timebase (@ 8 mhz f osc ) to 12-bit at timer f ltimer ltcsr2 tb2f 0 tb2ie 0 lttb2 8-bit timebase 0 0 8-bit autoreload register 8 ltcntr ltarr counter 2 counter 1 0 0 interrupt request 1
ST7L1 73/135 lite timer (cont?d) 11.3.3 functional description 11.3.3.1 timebase counter 1 the 8-bit value of counter 1 cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc /32. an overflow event occurs w hen the counter rolls over from f9h to 00h. if f osc = 8 mhz, then the time pe- riod between two counter overflow events is 1 ms. this period can be doubled by setting the tb bit in the ltcsr1 register. when counter 1 overflows, the tb1f bit is set by hardware and an interrupt request is generated if the tb1ie bit is set. the tb1f bit is cleared by software reading the ltcsr1 register. 11.3.3.2 input capture the 8-bit input capture register is used to latch the free-running upcounter (counter 1) 1 after a rising or falling edge is detected on the ltic pin. when an input capture occurs, the icf bit is set and the lticr1 register contains the msb of counter 1. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. the lticr is a read-only register and always con- tains the data from the last input capture. input capture is inhibited if the icf bit is set. 11.3.3.3 timebase counter 2 counter 2 is an 8-bit autoreload upcounter. it can be read by accessing the ltcntr register. after an mcu reset, it increments at a frequency of f osc /32 starting from the value stored in the ltarr register. a counter overflow event occurs when the counter rolls over from ffh to the ltarr reload value. so ftware can write a new value at any time in the ltarr register, this value will be automatically loade d in the counter when the next overflow occurs. when counter 2 overflows, the tb2f bit in the ltcsr2 register is set by hardware and an inter- rupt request is generated if the tb2ie bit is set. the tb2f bit is cleared by software reading the ltcsr2 register. figure 50. input capture timing diagram. 04h 8-bit counter 1 t 01h f osc /32 xxh 02h 03h 05h 06h 07h 04h ltic pin icf flag lticr register cleared 4s (@ 8 mhz f osc ) f cpu by s/w 07h reading ltic register 1
ST7L1 74/135 lite timer (cont?d) 11.3.4 low power modes 11.3.5 interrupts note: the tbxf and icf interrupt events are con- nected to separate interrupt vectors (see inter- rupts chapter). they generate an interrupt if the enable bit is set in the ltcsr1 or ltcsr2 register and the interrupt mask in the cc register is reset (rim instruction). 11.3.6 register description lite timer control/status register 2 (ltcsr2) read / write reset value: 0000 0000 (00h) bits 7:2 = reserved, must be kept cleared. bit 1 = tb2ie timebase 2 interrupt enable this bit is set and cleared by software. 0: timebase (tb2) interrupt disabled 1: timebase (tb2) interrupt enabled bit 0 = tb2f timebase 2 interrupt flag this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter 2 overflow 1: a counter 2 overflow has occurred lite timer auto reload register (ltarr) read / write reset value: 0000 0000 (00h) bits 7:0 = ar[7:0] counter 2 reload value these bits register is read/write by software. the ltarr value is automatica lly loaded into counter 2 (ltcntr) when an overflow occurs. lite timer counter 2 (ltcntr) read only reset value: 0000 0000 (00h) bits 7:0 = cnt[7:0] counter 2 reload value this register is read by software. the ltarr val- ue is automatically loaded into counter 2 (ltcn- tr) when an overflow occurs. lite timer control/status register (ltcsr1) read / write reset value: 0x00 0000 (x0h) bit 7 = icie interrupt enable this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled mode description slow no effect on lite timer (this peripheral is driven directly by f osc /32) wait no effect on lite timer active halt no effect on lite timer halt lite timer stops counting interrupt event event flag enable control bit exit from wait exit from active halt exit from halt timebase 1 event tb1f tb1ie yes yes no timebase 2 event tb2f tb2ie no ic event icf icie no 70 000000tb2ietb2f 70 ar7 ar7 ar7 ar7 ar3 ar2 ar1 ar0 70 cnt7 cnt7 cnt7 cnt7 cnt3 cnt2 cnt1 cnt0 70 icie icf tb tb1ie tb1f - - - 1
ST7L1 75/135 lite timer (cont?d) bit 6 = icf input capture flag this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, so ftware must initialize the icf bit by reading the lticr register bit 5 = tb timebase period selection this bit is set and cleared by software. 0: timebase period = t osc * 8000 (1ms @ 8 mhz) 1: timebase period = t osc * 16000 (2ms @ 8 mhz) bit 4 = tb1ie timebase interrupt enable this bit is set and cleared by software. 0: timebase (tb1) interrupt disabled 1: timebase (tb1) interrupt enabled bit 3 = tb1f timebase interrupt flag this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred bits 2:0 = reserved lite timer input capture register (lticr) read only reset value: 0000 0000 (00h) bits 7:0 = icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of t he 8-bit up-counter will be captured when a rising or falling edge occurs on the ltic pin. table 15. lite timer register map and reset values 70 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 address (hex.) register label 76543210 08 ltcsr2 reset value 000000 tb2ie 0 tb2f 0 09 ltarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0 0a ltcntr reset value cnt7 0 cnt6 0 cnt5 0 cnt4 0 cnt3 0 cnt2 0 cnt1 0 cnt0 0 0b ltcsr1 reset value icie 0 icf x tb 0 tb1ie 0 tb1f 0 000 0c lticr reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 1
ST7L1 76/135 on-chip peripherals (cont?d) 11.4 serial peripheral interface (spi) 11.4.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 11.4.2 main features full duplex synchronous transfers (on three lines) simplex synchronous transfers (on two lines) master or slave operation 6 master mode frequencies (f cpu /4 max.) f cpu /2 max. slave mode frequency (see note) ss management by software or hardware programmable clock polarity and phase end of transfer interrupt flag write collision, master mode fault and overrun flags note: in slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence. 11.4.3 general description figure 51 on page 77 shows the serial peripheral interface (spi) block diagram. there are three reg- isters: ? spi control register (spicr) ? spi control/status register (spicsr) ? spi data register (spidr) the spi is connected to external devices through four pins: ? miso: master in / slave out data ? mosi: master out / slave in data ? sck: serial clock out by spi masters and in- put by spi slaves ?ss : slave select: this input signal acts as a ?chip select? to let the spi master communicate with slaves indi- vidually and to avoid contention on the data lines. slave ss inputs can be driven by stand- ard i/o ports on the master device. 1
ST7L1 77/135 serial peripheral interface (spi) (cont?d) figure 51. serial peripheral interface block diagram spidr read buffer 8-bit shift register write read data/address bus spi spie spe mstr cpha spr0 spr1 cpol serial clock generator mosi miso ss sck control state spicr spicsr interrupt request master control spr2 0 7 0 7 spif wcol modf 0 ovr ssi ssm sod sod bit ss 1 0 1
ST7L1 78/135 serial peripheral interface (cont?d) 11.4.3.1 functional description a basic example of inte rconnections between a single master and a sing le slave is illustrated in figure 52 . the mosi pins are connected together and the miso pins are connected together. in this way data is transferred serially between master and slave (most significant bit first). the communication is alwa ys initiated by the mas- ter. when the master device transmits data to a slave device via mosi pin, the slave device re- sponds by sending data to the master device via the miso pin. this imp lies full duplex communica- tion with both data out and data in synchronized with the same clock signal (which is provided by the master device via the sck pin). to use a single data line, the miso and mosi pins must be connected at each node (in this case only simplex communication is possible). four possible data/clock timing relationships may be chosen (see figure 55 on page 81 ) but master and slave must be programmed with the same tim- ing mode. figure 52. single master/ single slave application 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit not used if ss is managed by software 1
ST7L1 79/135 serial peripheral interface (cont?d) 11.4.3.2 slave select management as an alternative to using the ss pin to control the slave select signal, the application can choose to manage the slave select signal by software. this is configured by the ssm bit in the spicsr regis- ter (see figure 54 ). in software management, the external ss pin is free for other application uses and the internal ss signal level is driven by writing to the ssi bit in the spicsr register. in master mode: ?ss internal must be held high continuously in slave mode: there are two cases depending on the data/clock timing relationship (see figure 53 ): if cpha = 1 (data latched on second clock edge): ?ss internal must be held low during the entire transmission. this implies that in single slave applications the ss pin either can be tied to v ss , or made free for standard i/o by manag- ing the ss function by software (ssm = 1 and ssi = 0 in the in the spicsr register) if cpha = 0 (data latched on first clock edge): ?ss internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift reg- ister. if ss is not pulled high, a write collision error will occur when the slave writes to the shift register (see section 11.4.5.3 ). figure 53. generic ss timing diagram figure 54. hardware/software slave select management mosi/miso master ss slave ss (if cpha = 0) slave ss (if cpha = 1) byte 1 byte 2 byte 3 1 0 ss internal ssm bit ssi bit ss external pin 1
ST7L1 80/135 serial peripheral interface (cont?d) 11.4.3.3 master mode operation in master mode, the serial clock is output on the sck pin. the clock frequency, polarity and phase are configured by software (refer to the description of the spicsr register). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). how to operate the spi in master mode to operate the spi in master mode, perform the following steps in order: 1. write to the spicr register: ? select the clock frequency by configuring the spr[2:0] bits. ? select the clock polarity and clock phase by configuring the cpol and cpha bits. figure 55 shows the four possible configurations. note: the slave must have the same cpol and cpha settings as the master. 2. write to the spicsr register: ? either set the ssm bit and set the ssi bit or clear the ssm bit and tie the ss pin high for the complete byte transmit sequence. 3. write to the spicr register: ? set the mstr and spe bits note: mstr and spe bits remain set only if ss is high). important note: if the spicsr register is not writ- ten first, the spicr register setting (mstr bit) may be not taken into account. the transmit sequence begins when software writes a byte in the spidr register. 11.4.3.4 master mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the mosi pin most sig- nificant bit first. when data transfer is complete: ? the spif bit is set by hardware. ? an interrupt request is generated if the spie bit is set and the interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spicsr register while the spif bit is set 2. a read to the spidr register note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. 11.4.3.5 slave mode operation in slave mode, the serial clock is received on the sck pin from the master device. to operate the spi in slave mode: 1. write to the spicsr register to perform the fol- lowing actions: ? select the clock polarity and clock phase by configuring the cpol and cpha bits (see figure 55 ). note: the slave must have the same cpol and cpha settings as the master. ? manage the ss pin as described in section 11.4.3.2 and figure 53 . if cpha = 1 ss must be held low continuously. if cpha = 0 ss must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. write to the spicr register to clear the mstr bit and set the spe bit to enable the spi i/o functions. 11.4.3.6 slave mode transmit sequence when software writes to the spidr register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the miso pin most sig- nificant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: ? the spif bit is set by hardware. ? an interrupt request is generated if spie bit is set and interrupt mask in the ccr register is cleared. clearing the spif bit is performed by the following software sequence: 1. an access to the spics r register while the spif bit is set 2. a write or a read to the spidr register notes: while the spif bit is set, all writes to the spidr register are inhibited until the spicsr reg- ister is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 11.4.5.2 ). 1
ST7L1 81/135 serial peripheral interface (cont?d) 11.4.4 clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits (see figure 55 ). note: the idle state of sck must correspond to the polarity selected in the spicsr register (by pulling up sck if cpol = 1 or pulling down sck if cpol = 0). the combination of the cpol clock polarity and cpha (clock phase) bits selects the data capture clock edge. figure 55 shows an spi transfer with the four com- binations of the cpha and cpol bits. the dia- gram may be interpreted as a master or slave tim- ing diagram where the sck pin, the miso pin and the mosi pin are directly connected between the master and the slave device. note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. figure 55. data clock timing diagram sck msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha = 1 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha = 0 note: this figure should not be used as a r eplacement for parametric information. refer to the electrical characteristics chapter. (from slave) (cpol = 1) sck (cpol = 0) sck (cpol = 1) sck (cpol = 0) 1
ST7L1 82/135 serial peripheral interface (cont?d) 11.4.5 error flags 11.4.5.1 master mode fault (modf) master mode fault occurs when the master de- vice?s ss pin is pulled low. when a master mode fault occurs: ? the modf bit is set and an spi interrupt re- quest is generated if the spie bit is set. ? the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. ? the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read access to the spicsr register while the modf bit is set. 2. a write to the spicr register. notes: to avoid any conflicts in an application with multiple slaves, the ss pin must be pulled high during the modf bit clearing sequence. the spe and mstr bits may be restored to their orig- inal state during or after this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device, the modf bit can not be set, but in a multimaster configuration the device can be in slave mode with the modf bit set. the modf bit indicates that there might have been a multimaster conflict and allows software to handle this using an interrupt routine and either perform a reset or return to an application default state. 11.4.5.2 overrun condition (ovr) an overrun condition occurs when the master de- vice has sent a data byte and the slave device has not cleared the spif bit issued from the previously transmitted byte. when an overrun occurs: ? the ovr bit is set and an interrupt request is generated if the spie bit is set. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the spidr register returns this byte. all other bytes are lost. the ovr bit is cleared by reading the spicsr register. 11.4.5.3 write collision error (wcol) a write collision occurs when the software tries to write to the spidr register while a data transfer is taking place with an external device. when this happens, the transfer continues uninterrupted and the software write will be unsuccessful. write collisions can occur both in master and slave mode. see also section 11.4.3.2 slave select management . note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the cpu oper- ation. the wcol bit in the spicsr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 56 ). figure 56. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read spicsr read spidr 2nd step spif = 0 wcol = 0 clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol = 0 read spicsr read spidr note: writing to the spidr regis- ter instead of reading it does not reset the wcol bit result result 1
ST7L1 83/135 serial peripheral interface (cont?d) 11.4.5.4 single master and multimaster configurations there are two types of spi systems: ? single master system ? multimaster system single master system a typical single master system may be configured using a device as the mast er and four devices as slaves (see figure 57 ). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line, the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previo us byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written to its spidr register. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multimaster system a multimaster system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multimaster system is principally handled by the mstr bit in the spicr register and the modf bit in the spicsr register. figure 57. single master / multiple slave configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave device slave device slave device slave device master device 1
ST7L1 84/135 serial peripheral interface (cont?d) 11.4.6 low power modes 11.4.6.1 using the spi to wake up the device from halt mode in slave configuration, the spi is able to wake up the device from halt mode through a spif inter- rupt. the data received is subsequently read from the spidr register when the software is running (interrupt vector fetch). if multiple data transfers have been performed before software clears the spif bit, then the ovr bit is set by hardware. note: when waking up from halt mode, if the spi remains in slave mode , it is recommended to perform an extra communications cycle to bring the spi from halt mode state to normal state. if the spi exits from slave mode, it returns to normal state immediately. caution: the spi can wake up the device from halt mode only if the slave select signal (exter- nal ss pin or the ssi bit in the spicsr register) is low when the device en ters halt mode. so, if slave selection is configured as external (see sec- tion 11.4.3.2 ), make sure the master drives a low level on the ss pin when the slave enters halt mode. 11.4.7 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi oper- ation resumes when the device is woken up by an interrupt with ?exit from halt mode? capability. the data received is subsequently read from the spidr r egister when the soft- ware is running (interrupt vector fetching). if several data are received before the wake- up event, then an overru n error is generated. this error can be detected after the fetch of the interrupt routine that woke up the device. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes yes master mode fault event modf no overrun error ovr 1
ST7L1 85/135 11.4.8 register description control register (spicr) read/write reset value: 0000 xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever an end of transfer event, master mode fault or over- run error occurs (spif = 1, modf = 1 or ovr = 1 in the spicsr register) bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.4.5.1 master mode fault (modf) ). the spe bit is cleared by reset, so the spi peripheral is not initia lly connected to the ex- ternal pins. 0: i/o pins free for general purpose i/o 1: spi i/o pin alternate functions enabled bit 5 = spr2 divider enable . this bit is set and cleared by software and is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 16 spi master mode sck frequency . 0: divider by 2 enabled 1: divider by 2 disabled note: this bit has no effect in slave mode. bit 4 = mstr master mode. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss =0 (see section 11.4.5.1 master mode fault (modf) ). 0: slave mode 1: master mode. the function of the sck pin changes from an input to an output and the func- tions of the miso and mosi pins are reversed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the idle state of the serial clock. the cpol bit affects both the master and slave modes. 0: sck pin has a low level idle state 1: sck pin has a high level idle state note : if cpol is changed at the communication byte boundaries, the spi must be disabled by re- setting the spe bit. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. note: the slave must have the same cpol and cpha settings as the master. bits 1:0 = spr[1:0] serial clock frequency. these bits are set and cleared by software. used with the spr2 bit, they select the baud rate of the spi serial clock sck output by the spi in master mode. note: these 2 bits have no effect in slave mode. table 16. spi master mode sck frequency 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /4 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1 1
ST7L1 86/135 serial peripheral interface (cont?d) control/status register (spicsr) read/write (some bits read only) reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag (read only). this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie = 1 in the spicr register. it is cleared by a software sequence (an access to the spicsr register followed by a write or a read to the spidr register). 0: data transfer is in progress or the flag has been cleared. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is se t, all writes to the spidr register are inhibited until the spicsr reg- ister is read. bit 6 = wcol write collision stat us (read only). this bit is set by hardware when a write to the spidr register is done during a transmit se- quence. it is cleared by a software sequence (see figure 56 ). 0: no write collision occurred 1: a write collision has been detected bit 5 = ovr s pi overrun error (read only). this bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the spidr register while spif = 1 (see section 11.4.5.2 ). an interrupt is generated if spie = 1 in the spicr register. the ovr bit is cleared by software reading the spicsr register. 0: no overrun error 1: overrun error detected bit 4 = modf mode fault flag (read only). this bit is set by hardware when the ss pin is pulled low in master mode (see section 11.4.5.1 master mode fault (modf) ). an spi interrupt can be generated if spie = 1 in the spicr register. this bit is cleared by a software sequence (an ac- cess to the spicsr register while modf = 1 fol- lowed by a write to the spicr register). 0: no master mode fault detected 1: a fault in master mode has been detected bit 3 = reserved, must be kept cleared. bit 2 = sod spi output disable. this bit is set and cleared by software. when set, it disables the alternate function of the spi output (mosi in master mode / miso in slave mode) 0: spi output enabled (if spe = 1) 1: spi output disabled bit 1 = ssm ss management. this bit is set and cleared by software. when set, it disables the alternate function of the spi ss pin and uses the ssi bit value instead. see section 11.4.3.2 slave select management . 0: hardware management (ss managed by exter- nal pin) 1: software management (internal ss signal con- trolled by ssi bit. external ss pin free for gener- al-purpose i/o) bit 0 = ssi ss internal mode. this bit is set and cleared by software. it acts as a ?chip select? by controlling the level of the ss slave select signal when the ssm bit is set. 0: slave selected 1: slave deselected data i/o register (spidr) read/write reset value: undefined the spidr register is used to transmit and receive data on the serial bus. in a master device, a write to this register will init iate transmission/reception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. while the spif bit is set, all writes to the spidr register are inhibited until the spicsr register is read. warning: a write to the spidr register places data directly into the shift register for transmission. a read to the spidr register returns the value lo- cated in the buffer and not the content of the shift register (see figure 51 ). 70 spif wcol ovr modf - sod ssm ssi 70 d7 d6 d5 d4 d3 d2 d1 d0 1
ST7L1 87/135 serial peripheral interface (cont?d) table 17. spi register map and reset values address (hex.) register label 76543210 0031h spidr reset value msb xxxxxxx lsb x 0032h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0033h spicsr reset value spif 0 wcol 0 ovr 0 modf 00 sod 0 ssm 0 ssi 0 1
ST7L1 88/135 on-chip peripherals (cont?d) 11.5 10-bit a/d converter (adc) 11.5.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to seve n multiplexed analog in- put channels (refer to dev ice pinout description) that allow the peripheral to convert the analog volt- age levels from up to seven different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 11.5.2 main features 10-bit conversion up to 7 channels with multiplexed input linear successive approximation data register (dr) which contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 58 . 11.5.3 functional description 11.5.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pinout description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 58. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ain6 analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 3 d1 d0 adcdrl 00 0 amp slow amp 0 r adc c adc hold control sel f adc f cpu 0 1 1 0 div 2 div 4 slow bit cal 1
ST7L1 89/135 10-bit a/d converter (adc) (cont?d) 11.5.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high-level voltage reference) then the conversion result is ffh in the a dcdrh register and 03h in the adcdrl register (with out overflow indication). if the input voltage (v ain ) is lower than v ssa (low- level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrh and ad- cdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this results in a loss of accuracy due to leak- age and sampling not being completed in the allot- ed time. 11.5.3.3 a/d conversion the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: ? select the ch[2:0] bits to assign the analog channel to convert. adc conversion mode in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? the result is in the adcdr registers. a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll the eoc bit 2. read adcdrl 3. read adcdrh. this clears eoc automati- cally. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this clears eoc automati- cally. 11.5.4 low-power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed and between single shot conversions. 11.5.5 interrupts none. mode description wait no effect on a/d converter halt a/d converter disabled. after wake-up from halt mode, the a/d converter requires a stabilization time t stab (see electrical characte ristics) before accu- rate conversions can be performed. 1
ST7L1 90/135 10-bit a/d converter (adc) (cont?d) 11.5.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by soft- ware reading the adcdrh register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to the table in the slow bit de- scription (adcdrl register). bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bits 4:3 = reserved. must be kept cleared. bits 2:0 = ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *the number of channels is device dependent. refer to the device pinout description. data register high (adcdrh) read only reset value: xxxx xxxx (xxh) bits 7:0 = d[9:2] msb of analog converted value amp control/data register low (ad- cdrl) read/write reset value: 0000 00xx (0xh) bits 7:5 = reserved. forced by hardware to 0. bit 4 = reserved . must be kept cleared. bit 3 = slow slow mode this bit is set and cleared by software. it is used together with the speed bi t in the adccsr regis- ter to configure the adc clock speed as shown on the table below. note: max f adc allowed = 4 mhz (see section 13.11 on page 122 ) bit 2 = reserved. must be kept cleared. bits 1:0 = d[1:0] lsb of analog converted value 70 eoc speed adon 0 0 ch2 ch1 ch0 channel pin* ch2 ch1 ch0 ain0 0 0 0 ain1 0 0 1 ain2 0 1 0 ain3 0 1 1 ain4 1 0 0 ain5 1 0 1 ain6 1 1 0 70 d9 d8 d7 d6 d5 d4 d3 d2 70 000 -slow-d1d0 f adc slow speed f cpu /2 00 f cpu 01 f cpu /4 1x 1
ST7L1 91/135 10-bit a/d converter (adc) (cont?d) table 18. adc register map and reset values address (hex.) register label 76543210 0034h adccsr reset value eoc 0 speed 0 adon 0 0 0 0 0 ch2 0 ch1 0 ch0 0 0035h adcdrh reset value d9 x d8 x d7 x d6 x d5 x d4 x d3 x d2 x 0036h adcdrl reset value 0 0 0 0 0 0 ampcal 0 slow 0 ampsel 0 d1 x d0 x 1
ST7L1 92/135 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be cla ssified in seven main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two submodes called long and short: ? long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 19. st7 addressing mode overview note : 1. at the time the instruction is ex ecuted, the program counter (pc) point s to the instruction following jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long ld a,[$10.w] 0000..ffff word short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long ld a,([$10.w],x) 0000..ffff word relative direct jrne loop pc-128/pc+127 1) + 1 indirect jrne [$10] 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 indirect bset [ $10],#7 00..ff byte + 2 direct relative btjt $10,#7,skip indirect btjt [$10], #7,skip 00..ff byte + 3 1
ST7L1 93/135 st7 addressing modes (cont?d) 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 12.1.2 immediate immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only 1 byte af- ter the opcode, but only allows 00 - ff addressing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three submodes: indexed (no offset) there is no offset (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two submodes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret subroutine return iret interrupt subroutine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations 1
ST7L1 94/135 st7 addressing modes (cont?d) 12.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 20. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative 1
ST7L1 95/135 12.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 ma in groups as illustrated in the following table: using a prebyte the instructions are described with 1 to 4 bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. 12.2.1 illegal opcode reset in order to provide enhanced robustness to the de- vice against unexpected be havior, a system of ille- gal opcode detection is implemented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, com- bined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf 1
ST7L1 96/135 instruction groups (cont?d) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > 1
ST7L1 97/135 instruction groups (cont?d) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z 1
ST7L1 98/135 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 13.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst con- ditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25c and t a =t a max (given by the selected tempera- ture range). data based on characterization results, design simulation and/or technology characteristics is in- dicated in the table footnotes and is not tested in production. based on characterization, the mini- mum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data is based on t a = 25c, v dd =5v (for the 4.5v v dd 5.5v voltage range) and v dd =3.3v (for the 3v v dd 3.6v voltage range). they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 59 . figure 59. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 60 . figure 60. pin input voltage c l st7 pin v in st7 pin
ST7L1 99/135 electrical characteristics (cont?d) 13.2 absolute ma ximum ratings stresses above those listed as ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 13.2.1 voltage characteristics 13.2.2 current characteristics 13.2.3 thermal characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an uni ntentional internal reset is generated or an unexpected change of the i/o configuration occurs (for exampl e, due to a corrupt ed program counter). to guarantee safe operation, this connection must be made through a pull-up or pull-down resistor (typical: 4.7k ? for reset , 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in ST7L1 100/135 electrical characteristics (cont?d) 13.3 operating conditions 13.3.1 general operating conditions t a = -40 to +125c, unless otherwise specified. figure 61. f clkin maximum operating frequency vs v dd supply voltage note: for further information on clock management block diagram for f clkin description, refer to figure 12 in section 7 on page 21 . symbol parameter conditions min max unit v dd supply voltage f osc = 16 mhz max t a = -40c to t a max 3.0 5.5 v f clkin external clock frequency on clkin pin v dd 3v 0 16 mhz t a ambient temperature range a suffix version -40 +85 c c suffix version +125 f clkin [mhz] supply voltage [v] 16 8 4 1 0 2.0 2.7 3.3 3.5 4.0 4.5 5.0 functionality not guaranteed in this area 5.5 functionality guaranteed in this area (unless otherwise stated in the tables of parametric data). 3.0 refer to section 13.3.4 on page 105 for pll oper- ating range.
ST7L1 101/135 operating conditions (cont?d) the rc oscillator and pl l characteristics are temperature-dependent. 13.3.1.1 operating condi tions (tested for t a = -40 to +125c) @ v dd = 4.5 to 5.5v notes: 1. if the rc oscillator clock is sele cted, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typi cally 100nf, between the v dd and v ss pins as close as possible to the st7 device. 2. see ?internal rc oscillator adjustment? on page 21 . 3. minimum value is obtained for hot temperatur e and max value is obtained for cold temperature. 4. data based on characterization results, not tested in production 5. measurement made with rc calibrated at 1 mhz. 6. guaranteed by design. 7. averaged over a 4ms period. after t he locked bit is set, a period of t stab is required to reach acc pll accuracy. 8. after the locked bit is set acc pll is maximum 10% until t stab has elapsed. see figure 11 on page 22 . figure 62. typical accur acy with rccr = rccr0 vs v dd = 4.5 to 5.5v and temperature symbol parameter conditions min typ max unit f rc 1) internal rc oscillator frequency rccr = ff (reset value), t a = 25c, v dd = 5v 700 khz rccr = rccr0 2 ) , t a = 25c, v dd = 5v 992 1000 1008 acc rc accuracy of internal rc oscillator with rccr = rccr0 2)3) t a = 25c, v dd = 5v -0.8 +0.8 % t a = 25c, v dd = 4.5 to 5.5v 4) -1 +1 t a = -40 to +125c, v dd = 4.5 to 5.5v 4) -3.5 +7 i dd(rc) rc oscillator current consumption t a = 25c, v dd =5v 600 4)5) a t su(rc) rc oscillator setup time 10 2) s f pll x8 pll input clock 1mhz t lock pll lock time 8) 2 ms t stab pll stabilization time 8) 4 acc pll x8 pll accuracy f rc =1 mhz@t a = 25c, v dd = 4.5 to 5.5v 4) 0.1 7) % f rc =1 mhz@t a = -40 to +125c, v dd =5v jit pll pll jitter ( ? f cpu /f cpu )1 6) i dd(pll) pll current consumption t a = 25c 600 4) a -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% 2.00% 2.50% 3.00% 3.50% 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 vdd (v) accuracy (%) -45 -10 0 25 90 110 130
ST7L1 102/135 operating conditions (cont?d) figure 63. f rc vs v dd and temperature for calibrated rccr0 13.3.1.2 operating condi tions (tested for t a = -40 to +125c) @ v dd = 3.0 to 3.6v 1 ) notes: 1. data based on characterization results, not tested in production. 2. if the rc oscillator clock is sele cted, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nf, bet ween the vdd and vss pins as close as possible to the st7 device. 3. see ?internal rc oscillator adjustment? on page 21 . 4. minimum value is obtained for hot temperature and maximum value is obtained for cold temperature. 5. measurement made with rc calibrated at 1 mhz. 6. guaranteed by design. 7. averaged over a 4ms period. after the locked bit is set, a period of tstab is required to reach accpll accuracy. 8. after the locked bit is set, accpll is maximum 10% until tstab has elapsed. see figure 11 on page 22 . symbol parameter 1) conditions min typ max unit f rc 2) internal rc oscillator fre- quency rccr = ff (reset value), t a = 25c, v dd = 3.3v 700 khz rccr = rccr1 3) , t a = 25c, v dd = 3.3v 992 1000 1008 acc rc accuracy of internal rc oscillator when calibrated with rccr = rccr1 3)4) t a = 25c, v dd = 3.3v -0.8 +0.8 % t a = 25c, v dd = 3 to 3.6v -1 +1 t a = -40 to +125c, v dd = 3 to 3.6v -5 +6.5 i dd(rc) rc oscillator current con- sumption t a = 25c, v dd = 3.3v 400 5) a t su(rc) rc oscillator setup time t a = 25c, v dd =3.3v 10 3) s f pll x4 pll input clock 0.7 mhz t lock pll lock time 8) 2 ms t stab pll stabilization time 8) 4 acc pll x4 pll accuracy f rc = 1 mhz @ t a = -40 to +125c, v dd = 3.3v 0.1 7) % f rc =1 mhz@t a = 25c, v dd = 3 to 3.6v 0.1 7) jit pll pll jitter ( ? f cpu /f cpu )1 6) i dd(pll) pll current consumption t a = 25c 190 a 0.98 0.985 0.99 0.995 1 1.005 1.01 1.015 1.02 1.025 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 vdd (v) frequency (mhz) -45 -10 0 25 90 110 130
ST7L1 103/135 operating conditions (cont?d) figure 64. typical accur acy with rccr = rccr1 vs v dd = 3 to 3.6v and temperature figure 65. f rc vs v dd and temperature for calibrated rccr1 -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) accuracy (%) -45 -10 0 25 90 110 130 0.98 0.985 0.99 0.995 1 1.005 1.01 3 3.1 3.2 3.3 3.4 3.5 3.6 vdd (v) frequency (mhz) -45 -10 0 25 90 110 130
ST7L1 104/135 operating conditions (cont?d) figure 66. pllx4 output vs clkin frequency note: f osc = f clkin /2*pll4 figure 67. pllx8 output vs clkin frequency note: f osc = f clkin /2*pll8 1.00 2.00 3.00 4.00 5.00 6.00 7.00 11.522.53 external input clock frequency (mhz) output frequency (mhz) 3.3 3 2.7 1.00 3.00 5.00 7.00 9.00 11.00 0.85 0.9 1 1.5 2 2.5 external input clock frequency (mhz) output frequency (mhz) 5.5 5 4.5 4
ST7L1 105/135 operating conditons (cont?d) 13.3.2 operating condi tions with low voltage detector (lvd) t a = -40 to +125c, unless otherwise specified. notes: 1. lvd functionality guar anteed only within the v dd operating range specified in section 13.3.1 on page 100 . 2. not tested in production. 3. not tested in production. the v dd rise time rate condition is needed to in sure a correct device power-on and lvd reset. when the v dd slope is outside these values, the lvd may not ensure a proper reset of the mcu. 4. based on design simulation. 5. use of lvd with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is rec- ommended to pull v dd down to 0v to ensure optimum restart conditions. refer to circuit example in figure 96 on page 119 and note 4. 13.3.3 auxiliary voltage detector (avd) thresholds t a = -40 to +125c, unless otherwise specified. notes: 1. lvd functionality guar anteed only within the v dd operating range specified in section 13.3.1 on page 100 . 2. data under characterizati on, not tested in production. 13.3.4 internal rc oscillator and pll the st7 internal clock can be supplie d by an internal rc oscillator and pll (selectable by option byte). notes: 1. x4 pll option only applicable on flash devices. symbol parameter conditions 1) min typ max unit v it+ (lvd) reset release threshold (v dd rise) 3.80 2) 4.20 4.60 v v it- (lvd) reset generation threshold (v dd fall) 3.70 4.00 4.35 2) v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) 200 mv vt por v dd rise time rate 3)5) 0.02 2) 100 2) ms/v t g(vdd) filtered glitch delay on v dd not detected by the lvd 150 4) ns i dd(lvd ) lvd/avd current consumption 200 a symbol parameter conditions 1) min typ max unit v it+ (avd) 1 ==> 0 avdf flag toggle threshold (v dd rise) tbd 2) 4.40 v v it- (avd) 0 ==> 1 avdf flag toggle threshold (v dd fall) 4.15 tbd 2) v hys avd voltage threshold hysteresis v it+ (avd) -v it- (avd) 170 mv ? v it- voltage drop between avd flag set and lvd reset activation v dd fall 0.15 v symbol parameter conditions min typ max unit v dd(rc) internal rc oscillator operating voltage refer to operating range of v dd with t a, section 13.3.1 on page 100 3.0 5.5 v v dd(x4pll) x4 pll operating voltage 1) 3.0 3.6 v dd(x8pll) x8 pll operating voltage 3.6 5.5 t startup pll start-up time 60 pll input clock (f pll ) cycles
ST7L1 106/135 electrical characteristics (cont?d) 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to obtain the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). 13.4.1 supply current t a = -40 to +125c, unless otherwise specified. notes: 1. cpu running with memory access, all i/o pi ns in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driv en by external square wave, lvd disabled. 2. all i/o pins in input m ode with a static value at v dd or v ss (no load), all peripherals in re set state; clock input (clkin) driven by external square wave, lvd disabled. 3. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in i nput mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripher als in reset state; clock input (clkin) dr iven by external square wave, lvd disabled. 5. all i/o pins in output m ode with a static value at v ss (no load), lvd disabl ed. data based on characterization results, tested in production at v dd max and f cpu max. 6. all i/o pins in input mode with a static value at v dd or v ss (no load). data tested in production at v dd max. and f cpu max. 7. this consumption refers to the halt period only and not t he associated run period which is software dependent. figure 68. typical i dd in run vs f cpu figure 69. typical i dd in run at f cpu = 8 mhz symbol parameter conditions typ max unit i dd supply current in run mode v dd =5.5v f cpu =8 mhz 1) 79 ma supply current in wait mode f cpu =8 mhz 2) 33.6 supply current in slow mode f cpu =250khz 3) 0.7 0.9 supply current in slow wait mode f cpu = 250 khz 4) 0.5 0.8 supply current in halt mode 5) -40c t a +125c 1 6 a supply current in awufh mode 6)7) -40c t a +125c 20 supply current in active halt mode -40c t a +125c ma 0 1 2 3 4 5 6 7 8 9 22.533.544.555.566.5 vdd (v) idd run (ma) vs freq (mhz) .5 1 2 4 6 8 note: graph displays data beyond the normal operating range of 3v - 5.5v note: graph displays data beyond the normal operating range of 3v - 5.5v 0 1 2 3 4 5 6 7 8 9 22.533.544.555.566.5 vdd (v) idd run (ma) at fcpu=8mhz 140c 90c 25c -5c -45c note: graph displays data beyond the normal operating range of 3v - 5.5v
ST7L1 107/135 supply current characteristics (cont?d) figure 70. typical i dd in slow vs f cpu figure 71. typical i dd in wait vs f cpu figure 72. typical i dd in wait at f cpu = 8 mhz figure 73. typical i dd in slow-wait vs f cpu figure 74. typical i dd vs temperature at v dd = 5v and f cpu = 8 mhz tbd 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 6 5 4 3.3 2.7 vdd (v) idd (ma) 250khz 125khz 62khz note: graph displays data beyond the normal operating range of 3v - 5.5v 0 0.5 1 1.5 2 2.5 3 3.5 4 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd wfi (ma) vs fcpu (mhz) 0.5 1 2 4 6 8 note: graph displays data beyond the normal operating range of 3v - 5.5v 0 0.5 1 1.5 2 2.5 3 3.5 4 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd wfi (ma) vs fcpu (mhz) 0.5 1 2 4 6 8 note: graph displays data beyond the normal operating range of 3v - 5.5v tb d 0.00 0.10 0.20 0.30 0.40 0.50 0.60 6 5 4 3.3 2.7 vdd (v) idd (ma) 250khz 125khz 62khz note: graph displays data beyond the normal operating range of 3v - 5.5v tbd 0.00 1.00 2.00 3.00 4.00 5.00 6.00 -45 25 90 110 temperature (c) idd (ma) run wait slow slow-wait
ST7L1 108/135 supply current characteristics (cont?d) 13.4.2 on-chip peripherals notes: 1. data based on a differential i dd measurement between reset configuration (timer stopped) and a timer running in pwm mode at f cpu =8 mhz. 2. data based on a differential i dd measurement between reset configurati on and a permanent spi master communica- tion (data sent equal to 55h). 3. data based on a differential i dd measurement between reset configur ation and continuous a/d conversions. 13.5 clock and timing characteristics subject to general operating conditions for v dd , f osc and t a . 13.5.1 general timings notes: 1. guaranteed by design. not tested in production. 2. data based on typical application software. 3. time measured between interrupt ev ent and interrupt vector fetch. dt c(inst) is the number of t cpu cycles needed to finish the current in struction execution. 13.5.2 auto wake-up from halt oscillator (awu) 1) notes: 1. guaranteed by design. not tested in production. symbol parameter conditions typ unit i dd(at) 12-bit auto-reload timer supply current 1) f cpu =4 mhz v dd = 3.3v 150 a f cpu =8 mhz v dd = 5v 1000 i dd(spi) spi supply current 2) f cpu =4 mhz v dd = 3.3v 50 f cpu =8 mhz v dd = 5v 200 i dd(adc) adc supply current when converting 3) f adc =4 mhz v dd = 3.3v 250 v dd = 5v 1100 symbol parameter 1) conditions min typ 2) max unit t c(inst) instruction cycle time f cpu =8 mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time 3) t v(it) = ? t c(inst) + 10 10 22 t cpu 1.25 2.75 s symbol parameter conditions min typ max unit f awu awu oscillator frequency 50 125 250 khz t rcsrt awu oscillator start-up time 50 s
ST7L1 109/135 clock and timing characteristics (cont?d) 13.5.3 crystal and ceramic resonator oscillators the st7 internal clock can be supplied with ten different crystal/ceramic resonator oscillators. all the information given in this paragraph are based on characterization results with specified typical external components. in the application, the reso- nator and the load capacitors must be placed as close as possible to the oscillator pins in order to minimize output distorti on and start-up stabiliza- tion time. refer to the crystal/ceramic resonator manufacturer for more details (frequency, pack- age, accuracy...). notes: 1. when pll is used, please refer to t he pll characteristics chapter and to ?supply, reset and clock manage- ment? on page 21 chapter (f crosc min. is 8 mhz with pll). 2. resonator characteristics are given by the ceramic resonator m anufacturer. for more information on these resonators, please consult www.murata.com. 3. smd = [-r0: plastic tape package ( ? =180mm)] lead = [-b0: bulk] 4. () means load capacitor built in resonator figure 75. typical application with a crystal or ceramic resonator symbol parameter conditions min typ max unit f crosc crystal oscillator frequency 1) 216mhz c l1 c l2 recommended load capacitance ver- sus equivalent serial resistance of the crystal or ceramic resonator (r s ) see table below pf supplier f crosc (mhz) typical ceramic resonators 2) cl1 4) (pf) cl2 4) (pf) rd ( ? ) supply voltage range (v) temperature range (c) type 3) reference murata 1 smd csbfb1m00j58-r0 220 220 2.2k 3.6 to 5.5 -40 to +125 lead csbla1m00j58-b0 2 smd cstcc2m00g56z-r0 (47) (47) 0 3.0 to 5.5 4 smd cstcr4m00g53z-r0 (15) (15) lead cstls4m00g53z-b0 8 smd cstce8m00g52z-r0 (10) (10) lead cstls8m00g53z-b0 (15) (15) 12 smd cstce12m0g52z-r0 (10) (10) 3.6 to 5.5 16 smd cstce16m0v51z-r0 (5) (5) lead cstls16m0x51z-b0 osc2 osc1 f osc c l1 c l2 i 2 st7 resonator when resonator with integrated capacitors r d
ST7L1 110/135 electrical characteristics (cont?d) 13.6 memory characteristics 13.6.1 ram and hardware registers t a = -40 to +125c, unless otherwise specified. 13.6.2 flash program memory t a = -40 to +85c, unless otherwise specified 13.6.3 eeprom data memory t a = -40 to +125c, unless otherwise specified notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). guaranteed by construction, not tested in production. 2. up to 32 bytes can be programmed at a time. 3. the data retention time increases when the t a decreases. 4. data based on reliability test results and monitored in production. 5. guaranteed by design. not tested in production. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit v dd operating voltage for flash write/erase refer to operating range of v dd with t a, section 13.3.1 on page 100 3.0 5.5 v t prog programming time for 1~32 bytes 2) t a =? 40 to +85c 5 10 ms programming time for 1.5 kbytes t a = 25c 0.24 0.48 s t ret 4) data retention t a = 55c 3) 20 years n rw write erase cycles t prog = 25c 1k cycles t prog = 85c 300 i dd supply current read / write / erase modes f cpu = 8 mhz, v dd = 5.5v 2.6 5) ma no read/no write mode 100 a power down mode / halt 0 0.1 symbol parameter conditions min typ max unit v dd operating voltage for eeprom write/ erase refer to operating range of v dd with t a, section 13.3.1 on page 100 3.0 5.5 v t prog programming time for 1~32 bytes t a =? 40 to +125c 5 10 ms t ret 4) data retention with 1k cycling (t prog = ? 40 to +125c t a = 55c 3) 20 years data retention with 10k cycling (t prog = ? 40 to +125c) 10 data retention with 100k cycling (t prog = ? 40 to +125c) 1
ST7L1 111/135 electrical characteristics (cont?d) 13.7 emc characteristics susceptibility tests are pe rformed on a sample ba- sis during product characterization. 13.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test confor ms with the iec 1000-4- 4 standard. a device reset allows normal operations to resume. the test results are given in the table be- low based on the ems levels and classes defined in application note an1709. 13.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore, it is recommended that emc software optimization and prequalification tests are made relative to the emc level requested for the user's application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. wh en unexpected behavior is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). 13.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling two leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/ 3 which specifies the board and the loading of each pin. notes: 1. data based on characterization results, not tested in production. symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a function- al disturbance v dd = 5v, t a = 25c, f osc = 8mhz, conforms to iec 1000-4-2 2b v fftb fast transient voltage burst li mits to be applied through 100pf on v dd and v dd pins to induce a f unctional disturbance v dd = 5v, t a = 25c, f osc = 8mhz, conforms to iec 1000-4-4 3b symbol parameter conditions monitored frequency band max vs [f osc /f cpu ]unit 8/4 mhz 16/8 mhz s emi peak level 1) v dd = 5v, t a = 25c, so20 package, conforming to sae j 1752/3 0.1 mhz to 30 mhz 15 20 db v 30 mhz to 130 mhz 17 21 130 mhz to 1 ghz 12 15 sae emi level 3 -
ST7L1 112/135 emc characteristics (cont?d) 13.7.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitiv ity. for more details, re- fer to application note an1181. 13.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test con- forms to the jesd22-a114a/a115a standard. absolute maximum ratings notes: 1. data based on characterization results, not tested in production. 13.7.3.2 static and dynamic latch-up lu : three complementar y static tests are required on six parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/ o pin) are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to application note an1181. electrical sensitivities notes: 1. class description: a class is an stmicr oelectronics internal specif ication. all its limits are higher than the jedec spec- ifications, which means when a device belongs to class a it e xceeds the jedec standard. cla ss b strictly covers all the jedec criteria (int ernational standard). symbol ratings condi tions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = 25c 8000 v v esd(mm) electro-static discharge voltage (machine model) 400 v esd(cdm) electro-static discharge vo ltage (charge device model) 1000 symbol parameter conditions class 1) lu static latch-up class t a = 25c t a = 125c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4 mhz, t a = 25c a
ST7L1 113/135 electrical characteristics (cont?d) 13.8 i/o port pin characteristics 13.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a , unless otherwise specified. notes: 1. data based on validation/design results. 2. configuration not recommended, all unused pi ns must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 76 ). static peak current val ue taken at a fixed v in value, based on design simulation and technology characteristics, not tested in production. this value depends on v dd and tem- perature values. 3. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 77 on page 115 ). 4. to generate an external interrupt, a minimum pulse width must be applied on an i/o port pin configured as an external interrupt source. figure 76. two typical applicat ions with unused i/o pin symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3xv dd v v ih input high level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis 1) 400 mv i l input leakage current v ss v in v dd 1 a i s static current c onsumption induced by each floating input pin 2) floating input mode 400 r pu weak pull-up equivalent resistor 3) v in = v ss v dd = 5v 50 120 250 k ? v dd = 3v 160 c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time 1) c l = 50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 1) 25 t w(it)in external interrupt pulse time 4) 1t cpu 10k ? unused i/o port st7 10k ? unused i/o port st7 v dd caution : during normal operation the iccclk pin must be pulled up, internally or externally (external pull-up of 10k mandatory in this is to avoid entering icc mode unexpectedly during a reset. noisy environment). note : i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc robustness and lower cost.
ST7L1 114/135 i/o port pin characteristics (cont?d) 13.8.2 output driving current subject to general operating conditions for v dd , f cpu and t a (-40 to +125c), unless otherwise specified. notes: 1. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 on page 99 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 13.2.2 on page 99 and the sum of i io (i/o ports and control pins) must not exceed i vdd . 3. not tested in production, based on characterization results. symbol parameter conditions min typ max unit v ol 1) output low level voltage for a standard i/o pin when eight pins are sunk at same time (see figure 78 ) v dd =5v i io =+5ma 1.0 v i io =+2ma 0.4 output low level voltage for a high sink i/o pin when four pins are sunk at same time (see figure 81 ) i io = +20ma 1.3 i io =+8ma 0.75 v oh 2) output high level voltage for an i/o pin when four pins are sourced at same time (see figure 87 ) i io =-5ma v dd -1.5 i io =-2ma v dd -0.8 v ol 1)3) output low level voltage for a standard i/o pin when eight pins are sunk at same time (see figure 77 ) v dd =3.3v i io =+2ma, t a +85c 0.5 output low level voltage for a high sink i/o pin when four pins are sunk at same time i io = +8ma, t a +85c v oh 2)3) output high level voltage for an i/o pin when four pins are sourced at same time ( figure 86 ) i io =-2ma, t a +85c v dd -0.8
ST7L1 115/135 i/o port pin characteristics (cont?d) figure 77. typical v ol at v dd = 3.3v (standard) figure 78. typical v ol at v dd = 5v (standard) figure 79. typical v ol at v dd = 3.3v (port c) figure 80. typical v ol at v dd =5v (port c) figure 81. typical v ol at v dd = 3.3v (high-sink) figure 82. typical v ol at v dd = 5v (high-sink) 0 0.1 0.2 0.3 0.4 0.5 0.6 00.511.522.533.5 iol (ma) vol std i/o (v) at vdd=3.3v 140c 90c 25c -5c -45c 0 0.2 0.4 0.6 0.8 1 1.2 012345678 iol (ma) vol std i/o (v) at vdd=5v 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 00.511.522.533.5 iol (ma) vol port c (v) at vdd=3.3v 140c 90c 25c -5c -45c 0 0.2 0.4 0.6 0.8 1 1.2 012345678 iol (ma) vol port c (v) at vdd=5v 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 024681012 iol (ma) vol high sink (v) at vdd=3.3v 140c 90c 25c -5c -45c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 5 10 15 20 25 30 35 iol (ma) vol high sink (v) at vdd=5v 140c 90c 25c -5c -45c
ST7L1 116/135 i/o port pin characteristics (cont?d) figure 83. typical v ol vs v dd (standard i/os) figure 84. typical v ol vs v dd (high-sink) figure 85. typical v ol vs v dd (port c) figure 86. typical v dd -v oh at v dd =3.3v figure 87. typical v dd -v oh at v dd =5v figure 88. typical v dd -v oh at v dd = 3.3v (hs) 0 0.1 0.2 0.3 0.4 0.5 0.6 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) vol std i/o (v) at iio=2ma 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) vol high sink (v) at iio=8ma 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) vol port c (v) at lio=2ma 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 00.511.522.533.5 iol (ma) |vdd-voh| std i/o (v) at vdd=3.3v 140c 90c 25c -5c -45c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 012345678 iol (ma) |vdd-voh| std i/o (v) at vdd=5v 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 0.5 1 1.5 2 2.5 3 3.5 iol (ma) |vdd-voh| high sink i/o (v) at vdd=3.3v 140c 90c 25c -5c -45c
ST7L1 117/135 i/o port pin characteristics (cont?d) figure 89. typical v dd -v oh at v dd = 5v (hs) figure 90. typical v dd -v oh at v dd =3.3v (port c) figure 91. typical v dd -v oh at v dd =5v (port c) figure 92. typical v dd -v oh vs v dd (standard) figure 93. typical v dd -v oh vs v dd (high sink) figure 94. typical v dd -v oh vs v dd (port c) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 012345678 iol (ma) |vdd-voh| high sink i/o (v) at vdd=5v 140c 90c 25c -5c -45c 0 0.2 0.4 0.6 0.8 1 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 iol (ma) |vdd-voh| port c (v) at vdd=3.3v 140c 90c 25c -5c -45c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 012345678 iol (ma) |vdd-voh| port c (v) at vdd=5v 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 22.533.544.555.566.5 vdd (v) |vdd-voh| std i/o (v) at loh=2ma 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 22.533.544.555.566.5 vdd (v) |vdd-voh| high sink i/o (v) at loh=2ma vs vdd 140c 90c 25c -5c -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 vdd (v) |vdd-voh| port c (v) at iio=2ma vs vdd 140c 90c 25c -5c -45c
ST7L1 118/135 electrical characteristics (cont?d) 13.9 control pin characteristics 13.9.1 asynchronous reset pin t a = -40 to +125c, unless otherwise specified. notes: 1. data based on characterization results, not tested in production. 2. the i io current sunk must always respect t he absolute maximum rating specified in section 13.2.2 on page 99 and the sum of i io (i/o ports and control pins) must not exceed i vss . 3. the r on pull-up equivalent resistor is based on a resistiv e transistor. specified for voltages on reset pin between v ilmax and v dd. 4. to guarantee the reset of the device, a minimum pulse must be applied to the reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. symbol parameter conditions min typ max unit v il 1) input low-level voltage v ss - 0.3 0.3xv dd v v ih 1) input high-level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis 1) 2 v ol 1) output low-level voltage 2) v dd =5v i io = +5ma, t a +125c 0.5 1.0 i io = +2ma, t a +125c 0.2 0.4 r on pull-up equivalent resistor 1)3) v dd = 5v 20 40 80 k ? v dd =3.3v 1) 40 70 120 t w(rstl)ou t generated reset pulse duratio n internal reset sources 30 s t h(rstl)in external reset pulse hold time 4) 20 t g(rstl)in filtered glitch duration 200 ns
ST7L1 119/135 control pin characteristics (cont?d) figure 95. reset pin protection when lvd is enabled 1)2)3)4) figure 96. reset pin protection when lvd is disabled 1) note 1: ? the reset network protects the device against parasitic resets. ? the output of the external reset circuit must have an open- drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). ? whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il maximum level specified in section 13.9.1 on page 118 . otherwise the reset is not taken into account internally. ? because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must en- sure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 13.2.2 on page 99 . note 2: when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to fi lter noise on the reset line. note 3: if a capacitive power supply is used, it is recommended to connect a 1m ? pull-down resistor to the reset pin to discharge any residual voltage induc ed by the capacitive effect of the power supply (this adds 5a to the power con- sumption of the mcu). note 4: tips when using the lvd: ? 1. check that all recommendations related to i ccclk and reset circuit have been applied (see caution in table 1 on page 5 and notes above) ? 2. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m ? pull-down on the reset pin. ? 3. the capacitors connected on the reset pin and also the power supply are key to avoi d any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. otherwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor.? note 5: please refer to section 12.2.1 on page 95 for more details on illegal opcode reset conditions. 0.01 f st7 pulse generator filter r on v dd internal reset reset external required 1m ? optional (note 3) watchdog lvd reset illegal opcode 5) 0.01 f external reset circuit user st7 pulse generator filter r on v dd internal reset watchdog illegal opcode 5) required
ST7L1 120/135 electrical characteristics (cont?d) 13.10 communication interface characteristics 13.10.1 spi - serial peripheral interface subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss , sck, mosi, miso). figure 97. spi slave timing diagram with cpha = 0 3) notes: 1. data based on design simulati on, not tested in production. 2. when no communication is on-going, the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability rel eased. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd . 4. depends on f cpu . for example, if f cpu = 8 mhz, then t cpu =1/f cpu = 125ns and t su(ss ) = 550ns. symbol parameter conditions min max unit f sck =1/ t c(sck) spi clock frequency master, f cpu =8mhz f cpu / 128 = 0.0625 f cpu /4=2 mhz slave, f cpu =8mhz 0 f cpu /2=4 t r(sck) spi clock rise and fall time see i/o port pin description t f(sck) t su(ss ) 1) ss setup time 4) slave (4 x t cpu )+50 ns t h(ss ) 1) ss hold time 120 t w(sckh) 1) sck high and low time master 100 t w(sckl) 1) slave 90 t su(mi) 1) data input setup time master 100 t su(si) 1) slave t h(mi) 1) data input hold time master t h(si) 1) slave t a(so) 1) data output access time slave 0120 t dis(so) 1) data output disable time 240 t v(so) 1) data output valid time slave (after enable edge) 120 t h(so) 1) data output hold time 0 t v(mo) 1) data output valid time master (after enable edge) 120 t h(mo) 1) data output hold time 0 ss input sck input cpha = 0 mosi input miso output cpha = 0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out seenote2 cpol = 0 cpol = 1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 bit1 in
ST7L1 121/135 communication interface characteristics (cont?d) figure 98. spi slave timing diagram with cpha = 1 1 ) figure 99. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd . 2. when no communication is on-going, t he alternate function capability of the spi?s data output line (mosi in master mode, miso in slave mode) is rel eased. in this case, the pin status depends on the i/o port configuration. ss input sck input cpha = 1 mosi input miso output cpha = 1 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol = 0 cpol = 1 t su(ss ) t h(ss ) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha = 0 mosi output miso input cpha = 0 cpha = 1 cpha = 1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) msb in msb out bit6 in bit6 out lsb out lsb in seenote2 seenote2 cpol = 0 cpol = 1 cpol = 0 cpol = 1 t r(sck) t f(sck) t h(mo) t v(mo)
ST7L1 122/135 electrical characteristics (cont?d) 13.11 10-bit adc characteristics subject to general operating conditions for v dd , f osc and t a unless otherwise specified. figure 100. typical application with adc notes: 1. unless otherwise specified, typical data is based on t a = 25c and v dd -v ss = 5v. they are given only as design guidelines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss . 3. any added external serial resist or downgrades the adc accuracy (espec ially for resistance greater than 10k ? ). data based on characterization resu lts, not tested in production. 4. the stabilization time of the ad c onverter is masked by the first t load . the first conversion after the enable is then always valid. related application notes: understanding and minimizing adc conversion errors (an1636) software techniques for compensating st7 adc errors (an1711) symbol parameter conditions min typ 1) max unit f adc adc clock frequency 4 mhz v ain conversion voltage range 2) v ssa v dda v r ain external input resistor 10 3) k ? c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 4) s t adc conversion time (sample+hold) 3.5 - sample capacitor loading time - hold conversion time 4 10 1/f adc i adc analog part 1 ma digital part 0.2 ainx st7 v dd i l 1 a v t 0.6v v t 0.6v c adc 6pf v ain r ain 10-bit a/d conversion
ST7L1 123/135 10-bit adc characteristics (cont?d) table 21. adc accuracy with 3v v dd 3.6v table 22. adc accuracy with 4.5v v dd 5.5v notes: 1. data based on characterization results over t he whole temperature range, monitored in production. 2. adc accuracy vs.negative injection current: injecting negat ive current on any of the anal og input pins may reduce the accuracy of the conversion bei ng performed on another analog input. the effect of negative injection curr ent on robust pins is specified in section 13.11 on page 122 any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 13.8 on page 113 does not affect the adc accuracy. 3. data based on characterization results, monitored in pr oduction to guarantee 99.73% within max value from -40c to +125c ( 3 distribution limits). figure 101. adc accuracy characteristics symbol parameter conditions typ max 3) unit |e t | total unadjusted error f cpu = 4 mhz, f adc = 2 mhz 1)2) 2.5 tbd lsb |e o | offset error 0.9 |e g | gain error 1.3 |e d | differential linearity error 1.8 |e l | integral linearity error symbol parameter conditions typ max unit |e t | total unadjusted error f cpu = 8 mhz, f adc = 4 mhz 1)2) 4 6 1) lsb |e o | offset error 3 5 1) |e g | gain error 1 4 1) |e d | differential linearity error 1.5 3 3) |e l | integral linearity error e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss
ST7L1 124/135 14 package characteristics in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level in- terconnect. the category of second level intercon- nect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to solder- ing conditions are also marked on the inner box la- bel. ecopack is an st tra demark. ecopack speci- fications are available at www.st.com. 14.1 package mechanical data figure 102. 20-pin plastic small outline package, 300-mil width table 23. thermal characteristics notes: 1. the maximum chip-junction temperatur e is based on technology characteristics. 2. the maximum power dissipati on is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an appl ication can be defined by the user with the formula: p d =p int +p port , where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation depending on the ports used in the application. dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.60 13.00 0.496 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 20 eh a a1 b e d c h x 45 l a symbol ratings value unit r thja package thermal resistance (junction to ambient) 85 c/w t jmax maximum junction temperature 1) 150 c p dmax power dissipation 2) 300 mw
ST7L1 125/135 package characteristics (cont?d 14.2 soldering information in accordance with the rohs european directive, all stmicroelectronics packages have been con- verted to lead-free technology, named eco- pack tm . ecopack tm packages are qualified according to the jedec std-020c compliant soldering profile. detailed information on the stmicroelectronics ecopack tm transition program is available on www.st.com/stonline/le adfree/, with specific technical application notes covering the main technical aspects related to lead-free conversion (an2033, an2034, an2035, an2036). backward and forward compatibility: the main difference between pb and pb-free sol- dering process is the temperature range. ? ecopack tm so packages are fully compatible with lead (pb) containing soldering process (see application note an2034) ? so pb-packages are compatible with lead-free soldering process, nevertheless it's the custom- er's duty to verify that the pb-packages maxi- mum temperature (mentioned on the inner box label) is compatible with their lead-free soldering temperature. table 24. soldering compatibility (wave and reflow soldering process) * assemblers must verify that the pb-package maximum temperature (mentioned on the inner box label) is compatible with their lead-free soldering process. package plating material devices pb solder paste pb-free solder paste so nipdau (nickel-palladium-gold) yes yes*
ST7L1 126/135 15 device configuration and ordering information each device is available for production in user pro- grammable versions (flash). ST7L1 devices are shipped to customers with a default program memory content (ffh). this implies that flash devices must be configured by the customer using the option bytes. 15.1 option bytes the 2 option bytes select the hardware configura- tion of the microcontroller. the option bytes are accessed only in program- ming mode (for example, using a standard st7 programming tool). option byte 0 opt7 = reserved , must always be 0. opt6 = reserved , must always be 1. opt5:4 = clksel clock source selection when the internal rc osc illator is not selected (option osc = 1), these option bits select the clock source: re sonator oscillator or external clock note: when the internal rc oscillator is selected, the clksel option bits must be kept at their de- fault value in order to select the 256 clock cycle delay (see section 7.5 ). opt3:2 = sec[1:0] sector 0 size definition these option bits indicate the size of sector 0 ac- cording to the following table. opt1 = fmp_r read-out protection readout protection, when selected, provides a protection against program memory content ex- traction and against write access to flash memo- ry. erasing the option bytes when the fmp_r op- tion is selected causes the whole memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.5 on page 12 for more de- tails 0: read-out protection off 1: read-out protection on opt0 = fmp_w flash write protection this option indicates if the flash program mem- ory is write protected. warning: when this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: write protection off 1: write protection on clock source port c clksel resonator ext. osc enabled/ port c disabled 00 external clock source: clkin on pb4 ext. osc disabled/ port c enabled 01 on pc0 1 1 reserved 1 0 sector 0 size sec1 sec0 0.5k 0 0 1k 1 2k 1 0 4k 1 option byte 0 70 option byte 1 70 res. res. clksel sec1 sec0 fmp r fmp w pll x4x8 pll off res. osc lvd1 lvd0 wdg sw wdg halt default value 0111010011 1 01111
ST7L1 127/135 option bytes (cont?d) option byte 1 opt7 = pllx4x8 pll factor selection (must be set to 1 for rom devices). 0: pllx4 1: pllx8 opt6 = plloff pll disable. 0: pll enabled 1: pll disabled (by-passed) opt5 = reserved. must be set to 1. opt4 = osc rc oscillator selection 0: rc oscillator on 1: rc oscillator off note: ? if the rc oscillator is selected, then to improve clock stability and frequency accuracy, it is rec- ommended to place a decoupling capacitor, typ- ically 100nf, between the v dd and v ss pins as close as possible to the st7 device. opt3:2 = lvd[1:0] low voltage detection selec- tion these option bits enable the voltage detection block (lvd and avd) with a selected threshold to the lvd and avd. opt1 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watch dog always enabled) 1: software (watchdog to be enabled by software) opt0 = wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode table 25. list of valid option combinations configuration lvd1 lvd0 lvd off 1 1 lvd on (highest voltage threshold) 0 operating conditions option bits v dd range clock source pll typ f cpu osc plloff pllx4x8 3.0 to 3.6v internal rc 1% off 1 mhz @ 3.3v 0 11 x4 4 mhz @ 3.3v 0 0 x8 - - - - external clock or resonator (depending on opt5:4 selection) off 0 to 4 mhz 1 11 x4 4 mhz 0 0 x8 - - - - 4.5 to 5.5v internal rc 1% off 1 mhz @ 5v 0 1 1 x4 - - - - x8 8 mhz @ 5v 0 0 1 external clock or resonator (depending on opt5:4 selection) off 0 to 8 mhz 1 1 1 x4 - - - - x8 8 mhz 1 0 1
ST7L1 128/135 device configuration an d ordering information (cont?d) 15.2 device ordering information table 26. supported part numbers part number program memory (bytes) ram (bytes) data eeprom (bytes) temperature range package st7fl15f1mae 4k flash 256 - -40c to +85c so20 st7fl15f1mce -40c to +125c st7fl19f1mae 128 -40c to +85c st7fl19f1mce -40c to +125c st7pl15f1mae 4k fastrom - -40c to +85c st7pl15f1mce -40c to +125c st7pl19f1mae 128 -40c to +85c st7pl19f1mce -40c to +125c ST7L15f1mae 4k rom - -40c to +85c ST7L15f1mce -40c to +125c ST7L19f1mae 128 -40c to +85c ST7L19f1mce -40c to +125c
ST7L1 129/135 ST7L1 fastrom and rom microcontroller option list (last update: august 2006) customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference fastrom code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *fastrom code name is assigned by stmicroelectronics. fastrom code must be sent in .s19 format. .hex extension cannot be processed. device type/memory size/pac kage (check only one option): conditioning (check only one option): special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ " (8 char. max.) authorized characters are letters, di gits, '.', '-', '/ ' and spaces only. temperature range: [ ] -40c to +85c [ ] -40c to +125c awuck selection [ ] 32 khz oscillator [ ] awu rc oscillator clock source selection: [ ] resonator: [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] external clock [ ] on pb4 [ ] on osc1 [ ] internal rc oscillator sector 0 size: [ ] 0.5k [ ] 1k [ ] 2k [ ] 4k readout protection: [ ] disabled [ ] enabled flash write protection [ ] disabled [ ] enabled pll [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] enabled (highest voltage threshold) watchdog selection: [ ] software ac tivation [ ] hard ware activation watchdog reset on halt: [ ] disabled [ ] enabled comments : supply operating range in the applic ation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . important note: not all configurations are available. see section 15.1 on page 126 for authorized option byte combinations. please download the latest versi on of this option list from: http://www.st.com/mcu > downloads > st7 microcontrollers > option list ------------------------------------ fastrom device: ------------------------------------- | | ----------------------------------------- 4k ----------------------------------------- so20: [ ] st7pl15 [ ] st7pl19 ------------------------------------ rom device: ------------------------------------- | | ----------------------------------------- 4k ----------------------------------------- so20: [ ] ST7L15 [ ] ST7L19 [ ] tape and reel [ ] tube
ST7L1 130/135 device configuration an d ordering information (cont?d) 15.3 development tools development tools for the st7 microcontrollers in- clude a complete range of hardware systems and software tools from stmicroelectronics and third- party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers. 15.3.1 evaluation tools and starter kits st offers complete, affordable starter kits and full-featured evaluation boards that allow you to evaluate microcontroller features and quickly start developing st7 applications. starter kits are com- plete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application. st eval- uation boards are open-design, embedded sys- tems, which are developed and documented to serve as references for your application design. they include sample application software to help you demonstrate, learn about and implement your st7?s features. 15.3.2 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assem- bler-linker toolchain, which are all seamlessly in- tegrated in the st7 integrated development envi- ronments in order to facilitate the debugging and fine-tuning of your application. the cosmic c compiler is available in a free version that outputs up to 16 kbytes of code. the range of hardware tools includes full-featured st7-emu3 series emulators, cost effective st7- dvp3 series emulators and the low-cost rlink in-circuit debugger/programmer. these tools are supported by the st7 toolset from stmicroelec- tronics, which includes the stvd7 integrated de- velopment environment (ide) with high-level lan- guage debugger, editor, project manager and inte- grated programming interface. 15.3.3 programming tools during the development cycle, the st7-dvp3 and st7-emu3 series emulators and the rlink pro- vide in-circuit programmi ng capability for program- ming the flash microcontroller on your application board. st also provides dedicated a low-cost dedicated in-circuit programmer, the st7-stick , as well as st7 socket boards which provide all the sockets required for programming any of the devices in a specific st7 sub-family on a platform that can be used with any tool with in-circuit programming ca- pability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solu- tions, which are ready to integrate into your pro- duction environment. 15.3.4 order codes for development and programming tools table 27 below lists the ordering codes for the ST7L1 development and programming tools. for additional ordering codes for spare parts and ac- cessories, refer to the online product selector at www.st.com/mcu. table 27. ST7L1 development and programming tools notes: 1. available from st or fr om raisonance, www.raisonance.com 2. usb connection to pc 3. add suffix /eu, /uk or /us fo r the power supply for your region 4. includes connection kit for dip16/so16 only. see ?how to order an emu or dvp? in st product and tool selection guide for connection kit ordering information 5. parallel port connection to pc 6. rlink with st7 tool set supported products in-circuit debugger, rlink series 1) emulator programming tool starter kit without demo board dvp series emu series in-circuit programmer st socket boards and epbs st7fl15 stx-rlink 2)6) st7mdt10-dvp3 4) st7mdt10-emu3 st7-stick 3)5) stx-rlink 6) st7sb10-123 3) st7fl19
ST7L1 131/135 15.4 st7 application notes table 28. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementat ion strategy with st7dali an1812 a high precision, low cost, single suppl y adc for positive and negative input voltages example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to g enerate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 moto r control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16-bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) impl ementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art an1947 st7mc pmac sine wave motor control software library
ST7L1 132/135 general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits vs industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite 1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improvi ng microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic dischar ge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 appl ications with internal rc oscillator an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the co smic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an 989 getting started with the st7 hiware c toolchain an1039 st7 math utility routines table 28. st7 application notes identification description
ST7L1 133/135 an1064 writing optimized hiware c language for st7 an1071 half duplex usb-to-serial bri dge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash micr ocontrollers in remote is p mode (in-situ programming) an1446 using the st72521 emulator to debug an st72324 target application an1477 emulated data eeprom with xflash memory an1478 porting an st7 panta project to codewarrior ide an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programmi ng (iap) drivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) im plementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac induction motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma- delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection during pwm on time by st7mc table 28. st7 application notes identification description
ST7L1 134/135 16 revision history table 29. revision history date revision main changes 16-aug-2006 1 initial release
ST7L1 135/135 please read carefully: information in this document is provided solely in conn ection with st products. st microelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corre ctions, modifications or improvements, to this docu- ment, and the products and services descr ibed herein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, select ion and use of the st products and services described herein, and st assumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwis e, to any intellectual property rights is granted under this document. if any part of this document refers to any th ird party products or services it shall not be deemed a li- cense grant by st for the use of such third party prod ucts or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms an d conditions of sale st disclaims any ex- press or implied warranty with respect to the use and/or sale of st products in- cluding without limi tation implied warr anties of merchantabili ty, fitness for a par- ticular purpose (and their equi valents under the laws of any jurisdiction), or in- fringement of any patent, copyright or other intellectual property right. unless expressly approved in wr iting by an authorized st representative, st prod- ucts are not recommended, aut horized or warranted for us e in military, air craft, space, life saving, or life sustaining appl ications, nor in pro ducts or systems where failure or malf unction may result in personal injury, death, or severe property or environmental damage. st pr oducts which are not specified as "automotive grade" may only be used in automotive applications at u ser?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this doc- ument shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any ma nner whatsoever, any liability of st. st and the st logo are trademarks or regist ered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectroni cs. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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